// ---------------------------------------------------------------------
//
//                   (C) COPYRIGHT 2005-2011 SYNOPSYS INC.
//                             ALL RIGHTS RESERVED
//
//  This software and the associated documentation are confidential and
//  proprietary to Synopsys Inc.  Your use or disclosure of this software
//  is subject to the terms and conditions of a written license agreement
//  between you or your company, and Synopsys, Inc.
//
//  The entire notice above must be reproduced on all authorized copies.
//
// -------------------------------------------------------------------------

//-----------------------------------------------------------------------------
// Filename    : DW_axi_x2h.v
// Created     : Tues Dec 21 20:00:00 GMT 2004
// Description : Top level AXI-to-AHB bridge.
//               A unidirectional bridge which is an AXI slave and
//               an AHB master.
//-----------------------------------------------------------------------------


module i_axi_x2h_DW_axi_x2h (/*AUTOARG*/
  // Outputs
  rdata, 
                   bresp, 
                   rresp, 
                   bid, 
                   rid, 
                   awready, 
                   wready, 
                   bvalid, 
                   arready,
                   rlast, 
                   rvalid, 
                   mhaddr, 
                   mhburst,
                   cactive, 
                   mhbusreq,
                   mhlock, 
                   mhprot, 
                   mhsize, 
                   mhtrans, 
                   mhwdata, 
                   mhwrite,
                   // Inputs
                   aclk, 
                   aresetn, 
                   awaddr, 
                   wdata, 
                   araddr, 
                   awvalid, 
                   wlast, 
                   wvalid,
                   bready, 
                   arvalid, 
                   rready, 
                   awburst, 
                   awlock, 
                   arburst, 
                   arlock, 
                   awsize,
                   awprot, 
                   arsize, 
                   arprot, 
                   awid, 
                   wid, 
                   awlen, 
                   awcache, 
                   wstrb, 
                   arid,
                   arlen, 
                   arcache, 
                   mhclk, 
                   mhresetn,
                   mhgrant,
                   mhrdata, 
                   mhready, 
                   mhresp
                   );
   // AXI slave inputs
  input                             aclk;
  input                             aresetn;
  input   [`X2H_AXI_ADDR_WIDTH-1:0] awaddr;
  input   [`X2H_AXI_DATA_WIDTH-1:0] wdata;
  input   [`X2H_AXI_ADDR_WIDTH-1:0] araddr;
  input                             awvalid;
  input                             wlast;
  input                             wvalid;
  input                             bready;
  input                             arvalid;
  input                             rready;
  input                       [1:0] awburst;
  input                       [1:0] awlock;
  input                       [1:0] arburst;
  input                       [1:0] arlock;
  input                       [2:0] awsize;
  input                       [2:0] awprot;
  input                       [2:0] arsize;
  input                       [2:0] arprot;
  input     [`X2H_AXI_ID_WIDTH-1:0] awid;
  input     [`X2H_AXI_ID_WIDTH-1:0] wid;
  input                       [3:0] awlen;
  input                       [3:0] awcache;
  input  [`X2H_AXI_WSTRB_WIDTH-1:0] wstrb;
  input     [`X2H_AXI_ID_WIDTH-1:0] arid;
  input                       [3:0] arlen;
  input                       [3:0] arcache;


  // AXI slave outputs
  output  [`X2H_AXI_DATA_WIDTH-1:0] rdata;
  output                      [1:0] bresp;
  output                      [1:0] rresp;
  output    [`X2H_AXI_ID_WIDTH-1:0] bid;
  output    [`X2H_AXI_ID_WIDTH-1:0] rid;
  output                            awready;
  output                            wready;
  output                            bvalid;
  output                            arready;
  output                            rlast;
  output                            rvalid;

  // used for low power in AXI
  output                            cactive;

  // AHB master inputs
  input                             mhclk;
  input                             mhresetn;
  input                             mhgrant;
  input   [`X2H_AHB_DATA_WIDTH-1:0] mhrdata;
  input                             mhready;
  input                       [1:0] mhresp;

  // AHB master outputs
  output  [`X2H_AHB_ADDR_WIDTH-1:0] mhaddr;
  output                      [2:0] mhburst;
  output                            mhbusreq;
  output                            mhlock;
  output                      [3:0] mhprot;
  output                      [2:0] mhsize;
  output                      [1:0] mhtrans;
  output  [`X2H_AHB_DATA_WIDTH-1:0] mhwdata;
  output                            mhwrite;



  // "Command" words
  wire      [`X2H_CMD_QUEUE_WIDTH-1:0] hcmd_queue_wd_int,
                                       cmd_queue_wd;

  // Write data (actually {WDATA,WSTRB,WLAST}
  wire     [`X2H_AXI_WDFIFO_WIDTH-1:0] awr_buff_wd,
                                       hwword_int;

  // Responses returned through write response, read data buffers
  wire                           [1:0] hwstatus_int,
                                       pop_resp_status_wd,
                                       hrstatus_int,
                                       arstatus_int;

  // IDs returned through write response, read data buffers
  wire         [`X2H_AXI_ID_WIDTH-1:0] hwid_int,
                                       pop_resp_id_wd,
                                       hrid_int,
                                       arid_int;

  // Read data
  wire      [`X2H_AXI_DATA_WIDTH-1:0] ardata_int,
                                       hrdata_int;

  // Amount of data (NOT SPACE!!) in read data buffer
  wire                           [7:0] hrdata_push_cnt;


  // Internal wires in the AXI-clock domain
  wire       awvalid_gtd,
             awready_int,
             wvalid_gtd,
             wready_int,
             arvalid_gtd,
             arready_int,
             resp_pop_rdy_n,
             pop_resp_n,
             wr_buff_push_rdy_n,
             push_write_buffer_n,
             arlast_int,
             pop_rdata_n,
             arvalid_int_n,
             cmd_push_af,
             cmd_queue_push_rdy_n,
             wr_push_cmd_queue_n,
             rd_push_cmd_queue_n;


  // Internal wires in the AHB-clock domain

  wire       hcmd_rdy_int_n,
             pop_hcmd_int_n,
             hwdata_rdy_int_n,
             pop_wdata_int_n,
             hresp_rdy_int_n,
             push_resp_int_n,
             hrlast_int,
             push_data_int_n,
             push_cmd_queue_n,
             mhgrant_int;


   assign mhgrant_int = mhgrant;

i_axi_x2h_DW_axi_x2h_slave
  U_AXI_SLAVE(
                  .awid(awid),
                  .awaddr(awaddr),
                  .awlen(awlen),
                  .awsize(awsize),
                  .awburst(awburst),
                  .awlock(awlock),
                  .awcache(awcache),
                  .awprot(awprot),
                  .awvalid(awvalid_gtd),
                  .awready(awready_int),
                  .wid(wid),
                  .wdata(wdata),
                  .wstrb(wstrb),
                  .wlast(wlast),
                  .wvalid(wvalid_gtd),
                  .wready(wready_int),
                  .bid(bid),
                  .bresp(bresp),
                  .bvalid(bvalid),
                  .bready(bready),

                  // the response buffer
                  .response_avail_n(resp_pop_rdy_n),
                  .pop_resp_n(pop_resp_n),
                  .pop_resp_word({pop_resp_status_wd,pop_resp_id_wd}),
                  // the write data buffer
                  .write_buffer_wd(awr_buff_wd),
                  .push_write_buffer_n(push_write_buffer_n),
                  .write_buff_rdy_n(wr_buff_push_rdy_n),
                  // read side
                  .arid(arid),
                  .araddr(araddr),
                  .arlen(arlen),
                  .arsize(arsize),
                  .arburst(arburst),
                  .arlock(arlock),
                  .arcache(arcache),
                  .arprot(arprot),
                  .arvalid(arvalid_gtd),
                  .arready(arready_int),
                  .rid(rid),
                  .rdata(rdata),
                  .rresp(rresp),
                  .rlast(rlast),
                  .rvalid(rvalid),
                  .rready(rready),
                  // the read data buffer
                  .arstatus_int(arstatus_int),
                  .arid_int(arid_int),
                  .arlast_int(arlast_int),
                  .ardata_int(ardata_int),
                  .pop_data_int_n(pop_rdata_n),
                  .arvalid_int_n(arvalid_int_n),
                  // the common command queue
                  .wr_push_comm_cmd_q_n(wr_push_cmd_queue_n),
                  .rd_push_comm_cmd_q_n(rd_push_cmd_queue_n),
                  .push_cmd_queue_n(push_cmd_queue_n),
                  .cmd_queue_wd(cmd_queue_wd),
                  .cmd_queue_rdy_n(cmd_queue_push_rdy_n));


i_axi_x2h_DW_axi_x2h_arb
 U_X2H_ARB (
                  .aclk(aclk),
                  .aresetn(aresetn),
                  // Outputs
                  .wvalid_gtd(wvalid_gtd),
                  .wready(wready),
                  .awvalid_gtd(awvalid_gtd),
                  .arvalid_gtd(arvalid_gtd),
                  .awready(awready),
                  .arready(arready),
                  // Inputs
                  .wvalid(wvalid),
                  .csysack(1'b1),
                  .csysack_ns(1'b1),
                  .awvalid(awvalid),
                  .arvalid(arvalid),
                  .wready_int(wready_int),
                  .cmd_queue_rdy_n(cmd_queue_push_rdy_n),
                  .cmd_push_af(cmd_push_af));


// FIFOs

i_axi_x2h_DW_axi_x2h_cmd_queue
 U_CMD_QUEUE (
               // the AXI slave side is pushing
               .clk_axi(aclk),
               .push_rst_n(aresetn),
               .acmd_queue_wd_int(cmd_queue_wd),
               .push_acmd_int_n(push_cmd_queue_n),
               .acmd_rdy_int_n(cmd_queue_push_rdy_n),
               .push_af(cmd_push_af),
               // the AHB Master Side is popping
               .clk_ahb(mhclk),
               .pop_rst_n(mhresetn),
               .pop_hcmd_int_n(pop_hcmd_int_n),
               .hcmd_queue_wd_int(hcmd_queue_wd_int),
               .hcmd_rdy_int_n(hcmd_rdy_int_n));

i_axi_x2h_DW_axi_x2h_write_data_buffer
 U_WR_DATA_BUFF (
             // AXI Slave Side is pushing
             .clk_axi(aclk),
             .push_rst_n(aresetn),
             .awword_int(awr_buff_wd),
             .push_awdata_int_n(push_write_buffer_n),
             .awdata_rdy_int_n(wr_buff_push_rdy_n),
              // the AHB Master Side is popping
             .clk_ahb(mhclk),
             .pop_rst_n(mhresetn),
             .hwword_int(hwword_int),
             .pop_wdata_int_n(pop_wdata_int_n),
             .hwdata_rdy_int_n(hwdata_rdy_int_n));


i_axi_x2h_DW_axi_x2h_resp_buffer
 U_RESP_BUFF (
               // the AXI slave side is popping
              .clk_axi(aclk),
              .pop_rst_n(aresetn),
              .awstatus_int(pop_resp_status_wd),
              .awid_int(pop_resp_id_wd),
              .pop_resp_int_n(pop_resp_n),
              .aresp_rdy_int_n(resp_pop_rdy_n),
               // the AHB Master Side is pushing
              .clk_ahb(mhclk),
              .push_rst_n(mhresetn),
              .hwstatus_int(hwstatus_int),
              .hwid_int(hwid_int),
              .push_resp_int_n(push_resp_int_n),
              .hresp_rdy_int_n(hresp_rdy_int_n));

i_axi_x2h_DW_axi_x2h_read_data_buffer
 U_RD_DATA_BUFF (
             // AXI Slave Side is popping
             .clk_axi(aclk),
             .pop_rst_n(aresetn),
             .arstatus_int(arstatus_int),
             .arid_int(arid_int),
             .arlast_int(arlast_int),
             .ardata_int(ardata_int),
             .pop_data_int_n(pop_rdata_n),
             .arvalid_int_n(arvalid_int_n),
              // the AHB Master Side is pushing
             .clk_ahb(mhclk),
             .push_rst_n(mhresetn),
             .hrstatus_int(hrstatus_int),
             .hrid_int(hrid_int),
             .hrlast_int(hrlast_int),
             .hrdata_int(hrdata_int),
             .push_data_int_n(push_data_int_n),
             .hrdata_push_cnt(hrdata_push_cnt));

// AHB Master interface

i_axi_x2h_DW_axi_x2h_ahb_master
  U_ahb_master (
             // Inputs
             .clk(mhclk),
             .rst_n(mhresetn),
             .hcmd_queue_wd_int(hcmd_queue_wd_int),
             .hcmd_rdy_int_n(hcmd_rdy_int_n),
             .hwword_int(hwword_int),
             .hwdata_rdy_int_n(hwdata_rdy_int_n),
             .hresp_rdy_int_n(hresp_rdy_int_n),
             .hrdata_push_cnt(hrdata_push_cnt),
             .mhgrant(mhgrant_int),
             .mhready(mhready),
             .mhresp(mhresp),
             .mhrdata(mhrdata),
             // Outputs
             .pop_hcmd_int_n(pop_hcmd_int_n),
             .pop_wdata_int_n(pop_wdata_int_n),
             .hwid_int(hwid_int),
             .hwstatus_int(hwstatus_int),
             .push_resp_int_n(push_resp_int_n),
             .hrid_int(hrid_int),
             .hrdata_int(hrdata_int),
             .hrstatus_int(hrstatus_int),
             .hrlast_int(hrlast_int),
             .push_data_int_n(push_data_int_n),
             .mhbusreq(mhbusreq),
             .mhlock(mhlock),
             .mhaddr(mhaddr),
             .mhsize(mhsize),
             .mhtrans(mhtrans),
             .mhburst(mhburst),
             .mhwrite(mhwrite),
             .mhprot(mhprot),
             .mhwdata(mhwdata) );





endmodule // DW_axi_x2h









