//-------------------------------------------------------------------
//
//  Filename      : vga_axi_top.v
//  Author        : Huang Lei Lei
//  Created       : 2015-08-09
//  Description   : vga top with axi if
//
//-------------------------------------------------------------------


module vga_axi_top(
  // global
  axi_clk         ,
  axi_rstn        ,
  vga_ctrl_clk    ,
  vga_ctrl_rstn   ,
  // control
  vga_en          ,
  // gm
  gm_maddr        ,
  gm_mburst       ,
  gm_mcache       ,
  gm_mdata        ,
  gm_mid          ,
  gm_mlen         ,
  gm_mlock        ,
  gm_mprot        ,
  gm_mread        ,
  gm_mready       ,
  gm_msize        ,
  gm_mwrite       ,
  gm_mwstrb       ,
  gm_saccept      ,
  gm_sdata        ,
  gm_sid          ,
  gm_slast        ,
  gm_sresp        ,
  gm_svalid       ,
  // vga_o
  oVGA_R          ,
  oVGA_G          ,
  oVGA_B          ,
  oVGA_H_SYNC     ,
  oVGA_V_SYNC     ,
  oVGA_SYNC       ,
  oVGA_BLANK      ,
  // fifo error
  vga_fifo_err
  );


//*** PARAMETER DECLARATION ****************************************************

  parameter     AXI_DW      = 'd64          ,
                AXI_AW      = 'd32          ,
                AXI_RID     = 'd1           ;


//*** INPUT/OUTPUT DECLARATION *************************************************

  // global
  input                     axi_clk         ;
  input                     axi_rstn        ;
  input                     vga_ctrl_clk    ;
  input                     vga_ctrl_rstn   ;

  // control
  input                     vga_en          ;

  // gm
  input                     gm_saccept      ;
  input   [AXI_DW-1   : 0]  gm_sdata        ;
  input   [3          : 0]  gm_sid          ;
  input                     gm_slast        ;
  input   [2          : 0]  gm_sresp        ;
  input                     gm_svalid       ;

  output  [AXI_AW-1   : 0]  gm_maddr        ;
  output  [1          : 0]  gm_mburst       ;
  output  [3          : 0]  gm_mcache       ;
  output  [AXI_DW-1   : 0]  gm_mdata        ;
  output  [3          : 0]  gm_mid          ;
  output  [3          : 0]  gm_mlen         ;
  output                    gm_mlock        ;
  output  [2          : 0]  gm_mprot        ;
  output                    gm_mread        ;
  output                    gm_mready       ;
  output  [2          : 0]  gm_msize        ;
  output                    gm_mwrite       ;
  output  [AXI_DW/8-1 : 0]  gm_mwstrb       ;

  // vga
  output  [7          : 0]  oVGA_R          ;
  output  [7          : 0]  oVGA_G          ;
  output  [7          : 0]  oVGA_B          ;
  wire    [9          : 0]  VGA_R           ;
  wire    [9          : 0]  VGA_G           ;
  wire    [9          : 0]  VGA_B           ;
  output                    oVGA_H_SYNC     ;
  output                    oVGA_V_SYNC     ;
  output                    oVGA_SYNC       ;
  output                    oVGA_BLANK      ;

  // fifo err
  output  [1          : 0]  vga_fifo_err    ;


//*** WIRE/REG DECLARATION *****************************************************

  wire    [9          : 0]  Red             ;
  wire    [9          : 0]  Green           ;
  wire    [9          : 0]  Blue            ;
  wire                      Request         ;
  wire                      en_vga          ;

  wire                      vga_ctrl_rstn0  ;


//*** MAIN BODY ****************************************************************

//*** VGA_AXI_IF *********************************

  vga_axi_if #(
    .AXI_DW             ( AXI_DW            ),
    .AXI_AW             ( AXI_AW            ),
    .AXI_RID            ( AXI_RID           )
    ) vga_axi_if0(
    // global
    .axi_clk            ( axi_clk           ),
    .axi_rstn           ( axi_rstn          ),
    .vga_ctrl_clk       ( vga_ctrl_clk      ),
    .vga_ctrl_rstn      ( vga_ctrl_rstn     ),
    // control
    .vga_en             ( vga_en            ),
    // gm
    .gm_maddr           ( gm_maddr          ),
    .gm_mburst          ( gm_mburst         ),
    .gm_mcache          ( gm_mcache         ),
    .gm_mdata           ( gm_mdata          ),
    .gm_mid             ( gm_mid            ),
    .gm_mlen            ( gm_mlen           ),
    .gm_mlock           ( gm_mlock          ),
    .gm_mprot           ( gm_mprot          ),
    .gm_mread           ( gm_mread          ),
    .gm_mready          ( gm_mready         ),
    .gm_msize           ( gm_msize          ),
    .gm_mwrite          ( gm_mwrite         ),
    .gm_mwstrb          ( gm_mwstrb         ),
    .gm_saccept         ( gm_saccept        ),
    .gm_sdata           ( gm_sdata          ),
    .gm_sid             ( gm_sid            ),
    .gm_slast           ( gm_slast          ),
    .gm_sresp           ( gm_sresp          ),
    .gm_svalid          ( gm_svalid         ),
    // vga
    .oEnable            ( Enable            ),
    .iRequest           ( Request           ),
    .oRed               ( Red               ),
    .oGreen             ( Green             ),
    .oBlue              ( Blue              ),
    // fifo err
    .vga_fifo_err       ( vga_fifo_err      )
    );


//*** VGA ****************************************

  VGA_Controller VGA_Controller0(
    .iCLK               ( vga_ctrl_clk      ),
    .iRST_N             ( Enable            ),
    // data in
    .iRed               ( Red               ),
    .iGreen             ( Green             ),
    .iBlue              ( Blue              ),
    .oRequest           ( Request           ),
    // data out
    .oVGA_R             ( VGA_R             ),
    .oVGA_G             ( VGA_G             ),
    .oVGA_B             ( VGA_B             ),
    .oVGA_H_SYNC        ( oVGA_H_SYNC       ),
    .oVGA_V_SYNC        ( oVGA_V_SYNC       ),
    .oVGA_SYNC          ( oVGA_SYNC         ),
    .oVGA_BLANK         ( oVGA_BLANK        )
    );

  assign oVGA_R = VGA_R[9:2];
  assign oVGA_G = VGA_G[9:2];
  assign oVGA_B = VGA_B[9:2];

endmodule
