#============================================================
# Build by Terasic System Builder
#============================================================

set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY "test_GFP"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:25:52 AUGUST 06,2015"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 780
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name SDC_FILE test_GFP.sdc
set_global_assignment -name SDC_FILE ./output_files/test_GFP.out.sdc
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"

set_location_assignment PIN_Y2 -to clk
set_location_assignment PIN_M21 -to rstn

set_location_assignment PIN_N21 -to key
set_location_assignment PIN_E21 -to led

set_location_assignment PIN_R6 -to sdram_addr[0]
set_location_assignment PIN_V8 -to sdram_addr[1]
set_location_assignment PIN_U8 -to sdram_addr[2]
set_location_assignment PIN_P1 -to sdram_addr[3]
set_location_assignment PIN_V5 -to sdram_addr[4]
set_location_assignment PIN_W8 -to sdram_addr[5]
set_location_assignment PIN_W7 -to sdram_addr[6]
set_location_assignment PIN_AA7 -to sdram_addr[7]
set_location_assignment PIN_Y5 -to sdram_addr[8]
set_location_assignment PIN_Y6 -to sdram_addr[9]
set_location_assignment PIN_R5 -to sdram_addr[10]
set_location_assignment PIN_AA5 -to sdram_addr[11]
set_location_assignment PIN_Y7 -to sdram_addr[12]
set_location_assignment PIN_U7 -to sdram_bank_addr[0]
set_location_assignment PIN_W3 -to sdram_dq[0]
set_location_assignment PIN_W2 -to sdram_dq[1]
set_location_assignment PIN_V4 -to sdram_dq[2]
set_location_assignment PIN_W1 -to sdram_dq[3]
set_location_assignment PIN_V3 -to sdram_dq[4]
set_location_assignment PIN_V2 -to sdram_dq[5]
set_location_assignment PIN_V1 -to sdram_dq[6]
set_location_assignment PIN_U3 -to sdram_dq[7]
set_location_assignment PIN_Y3 -to sdram_dq[8]
set_location_assignment PIN_Y4 -to sdram_dq[9]
set_location_assignment PIN_AB1 -to sdram_dq[10]
set_location_assignment PIN_AA3 -to sdram_dq[11]
set_location_assignment PIN_AB2 -to sdram_dq[12]
set_location_assignment PIN_AC1 -to sdram_dq[13]
set_location_assignment PIN_AB3 -to sdram_dq[14]
set_location_assignment PIN_AC2 -to sdram_dq[15]
set_location_assignment PIN_M8 -to sdram_dq[16]
set_location_assignment PIN_L8 -to sdram_dq[17]
set_location_assignment PIN_P2 -to sdram_dq[18]
set_location_assignment PIN_N3 -to sdram_dq[19]
set_location_assignment PIN_N4 -to sdram_dq[20]
set_location_assignment PIN_M4 -to sdram_dq[21]
set_location_assignment PIN_M7 -to sdram_dq[22]
set_location_assignment PIN_L7 -to sdram_dq[23]
set_location_assignment PIN_U5 -to sdram_dq[24]
set_location_assignment PIN_R7 -to sdram_dq[25]
set_location_assignment PIN_R1 -to sdram_dq[26]
set_location_assignment PIN_R2 -to sdram_dq[27]
set_location_assignment PIN_R3 -to sdram_dq[28]
set_location_assignment PIN_T3 -to sdram_dq[29]
set_location_assignment PIN_U4 -to sdram_dq[30]
set_location_assignment PIN_U1 -to sdram_dq[31]
set_location_assignment PIN_AE5 -to sdram_clk
set_location_assignment PIN_R4 -to sdram_bank_addr[1]
set_location_assignment PIN_V7 -to sdram_cas_n
set_location_assignment PIN_AA6 -to sdram_cke
set_location_assignment PIN_U2 -to sdram_dqm[0]
set_location_assignment PIN_W4 -to sdram_dqm[1]
set_location_assignment PIN_K8 -to sdram_dqm[2]
set_location_assignment PIN_N8 -to sdram_dqm[3]
set_location_assignment PIN_U6 -to sdram_ras_n
set_location_assignment PIN_T4 -to sdram_sel_n
set_location_assignment PIN_V6 -to sdram_we_n


#============================================================
# Design Files
#============================================================

set_global_assignment -name SEARCH_PATH ../../../include

set_global_assignment -name VERILOG_FILE ./test_GFP.v

set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_process.v

set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/axi.v

set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_rd/DW_axi_gm_cc_constants.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_rd/DW_axi_gm_bcm_params.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_rd/DW_axi_gm_bcm57.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_rd/DW_axi_gm_bcm06.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_rd/DW_axi_gm_bcm65.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_rd/DW_axi_gm_core.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_rd/DW_axi_gm.v
set_global_assignment -name VERILOG_FILE "../../../rtl/GFP_axi/gm_rd/DW_axi_gm-undef.v"

set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_wr/DW_axi_gm_cc_constants.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_wr/DW_axi_gm_bcm_params.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_wr/DW_axi_gm_bcm57.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_wr/DW_axi_gm_bcm06.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_wr/DW_axi_gm_bcm65.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_wr/DW_axi_gm_core.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/gm_wr/DW_axi_gm.v
set_global_assignment -name VERILOG_FILE "../../../rtl/GFP_axi/gm_wr/DW_axi_gm-undef.v"

set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_amba_constants.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_cc_constants.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_constants.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_bcm_params.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_bcm02.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_bcm01.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_bcm53.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_arbif.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_dcdr.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_dfltslv.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_ebt.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_gctrl.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_mask.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_mux.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_gating.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb_arb.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_ahb/DW_ahb.v
set_global_assignment -name VERILOG_FILE "../../../rtl/GFP_axi/i_ahb/DW_ahb-undef.v"

set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_cc_constants.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_constants.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_bcm_params.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_bcm01.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_bcm06.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_arbiter_fae.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_arbiter_fcfs.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_bcm57.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_arbiter_dp.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_busmux.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_busdemux.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_multibusmux.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_busmux_ohsel.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_systolcl.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_lcltosys.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_irs.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_irs_arbpl.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_dcdr.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_mca_reqhold.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_arbpl.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_arb.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_mp_tzone.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_mp_idmask.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_mp_addrch.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_mp_drespch.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_mp_wdatach.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_aw_mtile_dlock.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_mp.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_sp_addrch.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_lockdec.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_sp_lockarb.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_sp_drespch.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_fifo_s1_sf.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_sp_wrorder.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_sp_shrd_wrorder.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_sp_wdatach.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_sp.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_sp_shrd.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_mp_shrd.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_dfltslv.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_dlock_cnt.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_dlock_mux.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_lpfsm.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi_lp.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi/DW_axi.v
set_global_assignment -name VERILOG_FILE "../../../rtl/GFP_axi/i_axi/DW_axi-undef.v"

set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_cc_constants.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_ahb_cgen.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_ahb_cgen_logic.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_ahb_cpipe.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_ahb_fpipe.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_ahb_if.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_ahb_master.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_arb.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_cmd_queue.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_power_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_read_data_buffer.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_resp_buffer.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_slave.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_write_data_buffer.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_bcm57.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_bcm21.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_bcm07.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_bcm06.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_bcm05.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h_trcnt.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h.v
set_global_assignment -name VERILOG_FILE "../../../rtl/GFP_axi/i_axi_x2h/DW_axi_x2h-undef.v"

set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_params.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_bcm_params.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_constants.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_bcm01.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_hiu.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_hiu_afifo.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_fifo.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_hiu_acore.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_hiu_dfifo.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_hiu_dcore.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_hiu_ctl.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_hiu_rbuf.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_miu_sdc.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_miu_addrdec.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_miu_refctl.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_miu_cr.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_miu_dmc.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl_miu.v
set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_axi/i_memctl/DW_memctl.v

set_global_assignment -name VERILOG_FILE ../../../rtl/GFP_clkgen/GFP_clkgen.v

set_global_assignment -name QIP_FILE ../../../lib/ALTERA_DE2/pll/pll.qip
set_global_assignment -name QIP_FILE ../../../lib/ALTERA_DE2/tri/sdram_data_ctrl.qip

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name SLD_FILE "C:/Users/iamhll/Desktop/pj_a_general_fpga_platform/fpga/ALTERA_DE2/test_GFP_process/output_files/stp1_auto_stripped.stp"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top