/* --------------------------------------------------------------------
**
**                (C)  COPYRIGHT 2008 SYNOPSYS INC.
**                       ALL RIGHTS RESERVED
**
**  This software and the associated documentation are confidential
**  and proprietary to Synopsys, Inc.  Your use or disclosure of this
**  software is subject to the terms and conditions of a written
**  license agreement between you, or your company, and Synopsys, Inc.
**
**  The entire notice above must be reproduced on all authorized copies
**
** --------------------------------------------------------------------
**
** File     : DW_memctl_undef.v
**
** Abstract : This file undefines all macros that may have been defined
**            by this configuration of the DW_memctl
**
**            Users can add this file to thier simulator or synthesis
**            command line directly after the DW_memctl.lst file
**            to support multiple instances of the DW_memctl
**            component in their system
**
** NOTE:      This file is not automatically inserted into the
**            packaged simulation or synthesis environments
**
** --------------------------------------------------------------------
*/

`ifdef A8_FOR_PRECHARGE
  `undef A8_FOR_PRECHARGE
`endif

`ifdef ACT
  `undef ACT
`endif

`ifdef ACT_DSDC
  `undef ACT_DSDC
`endif

`ifdef ACT_SDC
  `undef ACT_SDC
`endif

`ifdef ADDR_FIFO_DEPTH
  `undef ADDR_FIFO_DEPTH
`endif

`ifdef AFIFO_IN_WIDTH
  `undef AFIFO_IN_WIDTH
`endif

`ifdef AFIFO_OUT_WIDTH
  `undef AFIFO_OUT_WIDTH
`endif

`ifdef AUTO_REF_DSDC
  `undef AUTO_REF_DSDC
`endif

`ifdef AUTO_REF_SDC
  `undef AUTO_REF_SDC
`endif

`ifdef BLOCK_SIZE0
  `undef BLOCK_SIZE0
`endif

`ifdef BLOCK_SIZE1
  `undef BLOCK_SIZE1
`endif

`ifdef BLOCK_SIZE2
  `undef BLOCK_SIZE2
`endif

`ifdef BLOCK_SIZE3
  `undef BLOCK_SIZE3
`endif

`ifdef BLOCK_SIZE4
  `undef BLOCK_SIZE4
`endif

`ifdef BLOCK_SIZE5
  `undef BLOCK_SIZE5
`endif

`ifdef BLOCK_SIZE6
  `undef BLOCK_SIZE6
`endif

`ifdef BLOCK_SIZE7
  `undef BLOCK_SIZE7
`endif

`ifdef BYT_CNT
  `undef BYT_CNT
`endif

`ifdef CAS_LATENCY
  `undef CAS_LATENCY
`endif

`ifdef CHIP_SEL0_ALIAS_ENABLE
  `undef CHIP_SEL0_ALIAS_ENABLE
`endif

`ifdef CHIP_SEL0_REMAP_ENABLE
  `undef CHIP_SEL0_REMAP_ENABLE
`endif

`ifdef CHIP_SEL1_ALIAS_ENABLE
  `undef CHIP_SEL1_ALIAS_ENABLE
`endif

`ifdef CHIP_SEL1_REMAP_ENABLE
  `undef CHIP_SEL1_REMAP_ENABLE
`endif

`ifdef CHIP_SELECT0_ALIAS_ADDRESS
  `undef CHIP_SELECT0_ALIAS_ADDRESS
`endif

`ifdef CHIP_SELECT0_BASE_ADDRESS
  `undef CHIP_SELECT0_BASE_ADDRESS
`endif

`ifdef CHIP_SELECT0_MEM
  `undef CHIP_SELECT0_MEM
`endif

`ifdef CHIP_SELECT0_REMAP_ADDRESS
  `undef CHIP_SELECT0_REMAP_ADDRESS
`endif

`ifdef CHIP_SELECT1_ALIAS_ADDRESS
  `undef CHIP_SELECT1_ALIAS_ADDRESS
`endif

`ifdef CHIP_SELECT1_BASE_ADDRESS
  `undef CHIP_SELECT1_BASE_ADDRESS
`endif

`ifdef CHIP_SELECT1_MEM
  `undef CHIP_SELECT1_MEM
`endif

`ifdef CHIP_SELECT1_REMAP_ADDRESS
  `undef CHIP_SELECT1_REMAP_ADDRESS
`endif

`ifdef CHIP_SELECT2_BASE_ADDRESS
  `undef CHIP_SELECT2_BASE_ADDRESS
`endif

`ifdef CHIP_SELECT2_MEM
  `undef CHIP_SELECT2_MEM
`endif

`ifdef CHIP_SELECT3_BASE_ADDRESS
  `undef CHIP_SELECT3_BASE_ADDRESS
`endif

`ifdef CHIP_SELECT3_MEM
  `undef CHIP_SELECT3_MEM
`endif

`ifdef CHIP_SELECT4_BASE_ADDRESS
  `undef CHIP_SELECT4_BASE_ADDRESS
`endif

`ifdef CHIP_SELECT4_MEM
  `undef CHIP_SELECT4_MEM
`endif

`ifdef CHIP_SELECT5_BASE_ADDRESS
  `undef CHIP_SELECT5_BASE_ADDRESS
`endif

`ifdef CHIP_SELECT5_MEM
  `undef CHIP_SELECT5_MEM
`endif

`ifdef CHIP_SELECT6_BASE_ADDRESS
  `undef CHIP_SELECT6_BASE_ADDRESS
`endif

`ifdef CHIP_SELECT6_MEM
  `undef CHIP_SELECT6_MEM
`endif

`ifdef CHIP_SELECT7_BASE_ADDRESS
  `undef CHIP_SELECT7_BASE_ADDRESS
`endif

`ifdef CHIP_SELECT7_MEM
  `undef CHIP_SELECT7_MEM
`endif

`ifdef CR_16RD1
  `undef CR_16RD1
`endif

`ifdef CR_16RD2
  `undef CR_16RD2
`endif

`ifdef CR_16WR1
  `undef CR_16WR1
`endif

`ifdef CR_16WR2
  `undef CR_16WR2
`endif

`ifdef CR_DONE
  `undef CR_DONE
`endif

`ifdef CR_IDLE
  `undef CR_IDLE
`endif

`ifdef CR_WR_DONE
  `undef CR_WR_DONE
`endif

`ifdef DEEP_POWER_DOWN_DSDC
  `undef DEEP_POWER_DOWN_DSDC
`endif

`ifdef DFIFO_IN_WIDTH
  `undef DFIFO_IN_WIDTH
`endif

`ifdef DFIFO_OUT_WIDTH
  `undef DFIFO_OUT_WIDTH
`endif

`ifdef DM_IDLE
  `undef DM_IDLE
`endif

`ifdef DM_READ
  `undef DM_READ
`endif

`ifdef DM_TERM
  `undef DM_TERM
`endif

`ifdef DM_WAIT
  `undef DM_WAIT
`endif

`ifdef DM_WRITE
  `undef DM_WRITE
`endif

`ifdef DYNAMIC_RAM_TYPE
  `undef DYNAMIC_RAM_TYPE
`endif

`ifdef EBI_INTERFACE
  `undef EBI_INTERFACE
`endif

`ifdef ENABLE_ADDRBUS_SHARING
  `undef ENABLE_ADDRBUS_SHARING
`endif

`ifdef ENABLE_DATABUS_SHARING
  `undef ENABLE_DATABUS_SHARING
`endif

`ifdef ENABLE_STATIC
  `undef ENABLE_STATIC
`endif

`ifdef ENCODED_BLOCK_SIZE0
  `undef ENCODED_BLOCK_SIZE0
`endif

`ifdef ENCODED_BLOCK_SIZE1
  `undef ENCODED_BLOCK_SIZE1
`endif

`ifdef ENCODED_BLOCK_SIZE2
  `undef ENCODED_BLOCK_SIZE2
`endif

`ifdef ENCODED_BLOCK_SIZE3
  `undef ENCODED_BLOCK_SIZE3
`endif

`ifdef ENCODED_BLOCK_SIZE4
  `undef ENCODED_BLOCK_SIZE4
`endif

`ifdef ENCODED_BLOCK_SIZE5
  `undef ENCODED_BLOCK_SIZE5
`endif

`ifdef ENCODED_BLOCK_SIZE6
  `undef ENCODED_BLOCK_SIZE6
`endif

`ifdef ENCODED_BLOCK_SIZE7
  `undef ENCODED_BLOCK_SIZE7
`endif

`ifdef ENCODED_CAS_LATENCY_1
  `undef ENCODED_CAS_LATENCY_1
`endif

`ifdef ENCODED_CHIP_SELECT0_MEM
  `undef ENCODED_CHIP_SELECT0_MEM
`endif

`ifdef ENCODED_CHIP_SELECT1_MEM
  `undef ENCODED_CHIP_SELECT1_MEM
`endif

`ifdef ENCODED_CHIP_SELECT2_MEM
  `undef ENCODED_CHIP_SELECT2_MEM
`endif

`ifdef ENCODED_CHIP_SELECT3_MEM
  `undef ENCODED_CHIP_SELECT3_MEM
`endif

`ifdef ENCODED_CHIP_SELECT4_MEM
  `undef ENCODED_CHIP_SELECT4_MEM
`endif

`ifdef ENCODED_CHIP_SELECT5_MEM
  `undef ENCODED_CHIP_SELECT5_MEM
`endif

`ifdef ENCODED_CHIP_SELECT6_MEM
  `undef ENCODED_CHIP_SELECT6_MEM
`endif

`ifdef ENCODED_CHIP_SELECT7_MEM
  `undef ENCODED_CHIP_SELECT7_MEM
`endif

`ifdef ENCODED_EXT_CAS_LATENCY_1
  `undef ENCODED_EXT_CAS_LATENCY_1
`endif

`ifdef ENCODED_EXT_T_XSR_1
  `undef ENCODED_EXT_T_XSR_1
`endif

`ifdef ENCODED_LOW_CAS_LATENCY_1
  `undef ENCODED_LOW_CAS_LATENCY_1
`endif

`ifdef ENCODED_LOW_FREQ_DEV_SET0
  `undef ENCODED_LOW_FREQ_DEV_SET0
`endif

`ifdef ENCODED_LOW_FREQ_DEV_SET1
  `undef ENCODED_LOW_FREQ_DEV_SET1
`endif

`ifdef ENCODED_LOW_FREQ_DEV_SET2
  `undef ENCODED_LOW_FREQ_DEV_SET2
`endif

`ifdef ENCODED_LOW_T_XSR_1
  `undef ENCODED_LOW_T_XSR_1
`endif

`ifdef ENCODED_NUM_INIT_REF_1
  `undef ENCODED_NUM_INIT_REF_1
`endif

`ifdef ENCODED_OPEN_BANKS_1
  `undef ENCODED_OPEN_BANKS_1
`endif

`ifdef ENCODED_PAGE_MODE_SET0
  `undef ENCODED_PAGE_MODE_SET0
`endif

`ifdef ENCODED_PAGE_MODE_SET1
  `undef ENCODED_PAGE_MODE_SET1
`endif

`ifdef ENCODED_PAGE_MODE_SET2
  `undef ENCODED_PAGE_MODE_SET2
`endif

`ifdef ENCODED_PAGE_SIZE_SET0
  `undef ENCODED_PAGE_SIZE_SET0
`endif

`ifdef ENCODED_PAGE_SIZE_SET1
  `undef ENCODED_PAGE_SIZE_SET1
`endif

`ifdef ENCODED_PAGE_SIZE_SET2
  `undef ENCODED_PAGE_SIZE_SET2
`endif

`ifdef ENCODED_READ_PIPE
  `undef ENCODED_READ_PIPE
`endif

`ifdef ENCODED_READY_MODE_SET0
  `undef ENCODED_READY_MODE_SET0
`endif

`ifdef ENCODED_READY_MODE_SET1
  `undef ENCODED_READY_MODE_SET1
`endif

`ifdef ENCODED_READY_MODE_SET2
  `undef ENCODED_READY_MODE_SET2
`endif

`ifdef ENCODED_REG_SELECT0
  `undef ENCODED_REG_SELECT0
`endif

`ifdef ENCODED_REG_SELECT1
  `undef ENCODED_REG_SELECT1
`endif

`ifdef ENCODED_REG_SELECT2
  `undef ENCODED_REG_SELECT2
`endif

`ifdef ENCODED_REG_SELECT3
  `undef ENCODED_REG_SELECT3
`endif

`ifdef ENCODED_REG_SELECT4
  `undef ENCODED_REG_SELECT4
`endif

`ifdef ENCODED_REG_SELECT5
  `undef ENCODED_REG_SELECT5
`endif

`ifdef ENCODED_REG_SELECT6
  `undef ENCODED_REG_SELECT6
`endif

`ifdef ENCODED_REG_SELECT7
  `undef ENCODED_REG_SELECT7
`endif

`ifdef ENCODED_S_BANK_ADDR_WIDTH_1
  `undef ENCODED_S_BANK_ADDR_WIDTH_1
`endif

`ifdef ENCODED_S_COL_ADDR_WIDTH_1
  `undef ENCODED_S_COL_ADDR_WIDTH_1
`endif

`ifdef ENCODED_S_DATA_WIDTH
  `undef ENCODED_S_DATA_WIDTH
`endif

`ifdef ENCODED_SM_DATA_WIDTH_SET0
  `undef ENCODED_SM_DATA_WIDTH_SET0
`endif

`ifdef ENCODED_SM_DATA_WIDTH_SET1
  `undef ENCODED_SM_DATA_WIDTH_SET1
`endif

`ifdef ENCODED_SM_DATA_WIDTH_SET2
  `undef ENCODED_SM_DATA_WIDTH_SET2
`endif

`ifdef ENCODED_SM_READ_PIPE_SET0
  `undef ENCODED_SM_READ_PIPE_SET0
`endif

`ifdef ENCODED_SM_READ_PIPE_SET1
  `undef ENCODED_SM_READ_PIPE_SET1
`endif

`ifdef ENCODED_SM_READ_PIPE_SET2
  `undef ENCODED_SM_READ_PIPE_SET2
`endif

`ifdef ENCODED_S_READY_VALID
  `undef ENCODED_S_READY_VALID
`endif

`ifdef ENCODED_S_ROW_ADDR_WIDTH_1
  `undef ENCODED_S_ROW_ADDR_WIDTH_1
`endif

`ifdef ENCODED_T_AS_SET0
  `undef ENCODED_T_AS_SET0
`endif

`ifdef ENCODED_T_AS_SET1
  `undef ENCODED_T_AS_SET1
`endif

`ifdef ENCODED_T_AS_SET2
  `undef ENCODED_T_AS_SET2
`endif

`ifdef ENCODED_T_BTA_SET0
  `undef ENCODED_T_BTA_SET0
`endif

`ifdef ENCODED_T_BTA_SET1
  `undef ENCODED_T_BTA_SET1
`endif

`ifdef ENCODED_T_BTA_SET2
  `undef ENCODED_T_BTA_SET2
`endif

`ifdef ENCODED_T_INIT
  `undef ENCODED_T_INIT
`endif

`ifdef ENCODED_T_PRC_SET0_1
  `undef ENCODED_T_PRC_SET0_1
`endif

`ifdef ENCODED_T_PRC_SET1_1
  `undef ENCODED_T_PRC_SET1_1
`endif

`ifdef ENCODED_T_PRC_SET2_1
  `undef ENCODED_T_PRC_SET2_1
`endif

`ifdef ENCODED_T_RAS_MIN_1
  `undef ENCODED_T_RAS_MIN_1
`endif

`ifdef ENCODED_T_RC_1
  `undef ENCODED_T_RC_1
`endif

`ifdef ENCODED_T_RCAR_1
  `undef ENCODED_T_RCAR_1
`endif

`ifdef ENCODED_T_RCD_1
  `undef ENCODED_T_RCD_1
`endif

`ifdef ENCODED_T_RC_SET0_1
  `undef ENCODED_T_RC_SET0_1
`endif

`ifdef ENCODED_T_RC_SET1_1
  `undef ENCODED_T_RC_SET1_1
`endif

`ifdef ENCODED_T_RC_SET2_1
  `undef ENCODED_T_RC_SET2_1
`endif

`ifdef ENCODED_T_REF
  `undef ENCODED_T_REF
`endif

`ifdef ENCODED_T_RP_1
  `undef ENCODED_T_RP_1
`endif

`ifdef ENCODED_T_RPD
  `undef ENCODED_T_RPD
`endif

`ifdef ENCODED_T_WP_SET0_1
  `undef ENCODED_T_WP_SET0_1
`endif

`ifdef ENCODED_T_WP_SET1_1
  `undef ENCODED_T_WP_SET1_1
`endif

`ifdef ENCODED_T_WP_SET2_1
  `undef ENCODED_T_WP_SET2_1
`endif

`ifdef ENCODED_T_WR_1
  `undef ENCODED_T_WR_1
`endif

`ifdef ENCODED_T_WR_SET0
  `undef ENCODED_T_WR_SET0
`endif

`ifdef ENCODED_T_WR_SET1
  `undef ENCODED_T_WR_SET1
`endif

`ifdef ENCODED_T_WR_SET2
  `undef ENCODED_T_WR_SET2
`endif

`ifdef ENCODED_T_WTR_1
  `undef ENCODED_T_WTR_1
`endif

`ifdef ENCODED_T_XSR_1
  `undef ENCODED_T_XSR_1
`endif

`ifdef EXTENDED_MODE_REG
  `undef EXTENDED_MODE_REG
`endif

`ifdef FL_ACT
  `undef FL_ACT
`endif

`ifdef FL_IDLE
  `undef FL_IDLE
`endif

`ifdef FL_INIT
  `undef FL_INIT
`endif

`ifdef FL_LCR
  `undef FL_LCR
`endif

`ifdef FL_RD
  `undef FL_RD
`endif

`ifdef FL_READY
  `undef FL_READY
`endif

`ifdef FL_RP
  `undef FL_RP
`endif

`ifdef FL_RST
  `undef FL_RST
`endif

`ifdef FL_WR
  `undef FL_WR
`endif

`ifdef HADDR_SIZE32
  `undef HADDR_SIZE32
`endif

`ifdef H_ADDR_WIDTH
  `undef H_ADDR_WIDTH
`endif

`ifdef HARD_WIRE_CIPSELECT_PARAMETRS
  `undef HARD_WIRE_CIPSELECT_PARAMETRS
`endif

`ifdef HARD_WIRE_SDRAM_PARAMETERS
  `undef HARD_WIRE_SDRAM_PARAMETERS
`endif

`ifdef HARD_WIRE_STATIC_PARAMETERS
  `undef HARD_WIRE_STATIC_PARAMETERS
`endif

`ifdef HARD_WIRE_SYNCFLASH_PARAMETERS
  `undef HARD_WIRE_SYNCFLASH_PARAMETERS
`endif

`ifdef H_DATA_WIDTH
  `undef H_DATA_WIDTH
`endif

`ifdef HIGHER_ADDR_FOR_BANKS
  `undef HIGHER_ADDR_FOR_BANKS
`endif

`ifdef HIGHER_ADDR_FOR_SF_BANKS
  `undef HIGHER_ADDR_FOR_SF_BANKS
`endif

`ifdef IDLE
  `undef IDLE
`endif

`ifdef IDLE_DSDC
  `undef IDLE_DSDC
`endif

`ifdef IDLE_SDC
  `undef IDLE_SDC
`endif

`ifdef IN_CKE_DSDC
  `undef IN_CKE_DSDC
`endif

`ifdef INCLUDE_INTERNAL_TESTS
  `undef INCLUDE_INTERNAL_TESTS
`endif

`ifdef IN_DONE
  `undef IN_DONE
`endif

`ifdef IN_LD_EMR_DSDC
  `undef IN_LD_EMR_DSDC
`endif

`ifdef IN_LD_EMR_SDC
  `undef IN_LD_EMR_SDC
`endif

`ifdef IN_LD_MR1_DSDC
  `undef IN_LD_MR1_DSDC
`endif

`ifdef IN_LD_MR2_DSDC
  `undef IN_LD_MR2_DSDC
`endif

`ifdef IN_LD_MR_SDC
  `undef IN_LD_MR_SDC
`endif

`ifdef IN_PREC1_DSDC
  `undef IN_PREC1_DSDC
`endif

`ifdef IN_PREC2_DSDC
  `undef IN_PREC2_DSDC
`endif

`ifdef IN_PREC_SDC
  `undef IN_PREC_SDC
`endif

`ifdef IN_REF_DSDC
  `undef IN_REF_DSDC
`endif

`ifdef IN_REF_SDC
  `undef IN_REF_SDC
`endif

`ifdef IN_RP
  `undef IN_RP
`endif

`ifdef IN_START
  `undef IN_START
`endif

`ifdef IN_START_DSDC
  `undef IN_START_DSDC
`endif

`ifdef IN_START_SDC
  `undef IN_START_SDC
`endif

`ifdef INT_REF_DSDC
  `undef INT_REF_DSDC
`endif

`ifdef INT_REF_SDC
  `undef INT_REF_SDC
`endif

`ifdef INT_RF_PREC_DSDC
  `undef INT_RF_PREC_DSDC
`endif

`ifdef INT_RF_PREC_SDC
  `undef INT_RF_PREC_SDC
`endif

`ifdef IN_WAIT
  `undef IN_WAIT
`endif

`ifdef IN_WAIT_DSDC
  `undef IN_WAIT_DSDC
`endif

`ifdef IN_WAIT_SDC
  `undef IN_WAIT_SDC
`endif

`ifdef LOAD_EMR_DSDC
  `undef LOAD_EMR_DSDC
`endif

`ifdef LOAD_EMR_SDC
  `undef LOAD_EMR_SDC
`endif

`ifdef LOAD_MR
  `undef LOAD_MR
`endif

`ifdef LOAD_MR_DSDC
  `undef LOAD_MR_DSDC
`endif

`ifdef LOAD_MR_SDC
  `undef LOAD_MR_SDC
`endif

`ifdef LOW_FREQ_DEV_SET0
  `undef LOW_FREQ_DEV_SET0
`endif

`ifdef LOW_FREQ_DEV_SET1
  `undef LOW_FREQ_DEV_SET1
`endif

`ifdef LOW_FREQ_DEV_SET2
  `undef LOW_FREQ_DEV_SET2
`endif

`ifdef M_ADDR_WIDTH
  `undef M_ADDR_WIDTH
`endif

`ifdef MAX_S_BANK_ADDR_WIDTH
  `undef MAX_S_BANK_ADDR_WIDTH
`endif

`ifdef MAX_S_DATA_WIDTH
  `undef MAX_S_DATA_WIDTH
`endif

`ifdef MAX_SM_DATA_WIDTH
  `undef MAX_SM_DATA_WIDTH
`endif

`ifdef M_DATA_WIDTH
  `undef M_DATA_WIDTH
`endif

`ifdef MEMCTL_COMP_TYPE
  `undef MEMCTL_COMP_TYPE
`endif

`ifdef MEMCTL_COMP_VERSION
  `undef MEMCTL_COMP_VERSION
`endif

`ifdef MEMCTL_ENCRYPT
  `undef MEMCTL_ENCRYPT
`endif

`ifdef MEMCTL_REG_SM_READY
  `undef MEMCTL_REG_SM_READY
`endif

`ifdef MEMCTL_USE_FOUNDATION_IS_ONE
  `undef MEMCTL_USE_FOUNDATION_IS_ONE
`endif

`ifdef MOBILE_DDR_SDRAM
  `undef MOBILE_DDR_SDRAM
`endif

`ifdef MODEL_DWIDTH_CS0
  `undef MODEL_DWIDTH_CS0
`endif

`ifdef MODEL_DWIDTH_CS1
  `undef MODEL_DWIDTH_CS1
`endif

`ifdef MODEL_DWIDTH_CS2
  `undef MODEL_DWIDTH_CS2
`endif

`ifdef MODEL_DWIDTH_CS3
  `undef MODEL_DWIDTH_CS3
`endif

`ifdef MODEL_DWIDTH_CS4
  `undef MODEL_DWIDTH_CS4
`endif

`ifdef MODEL_DWIDTH_CS5
  `undef MODEL_DWIDTH_CS5
`endif

`ifdef MODEL_DWIDTH_CS6
  `undef MODEL_DWIDTH_CS6
`endif

`ifdef MODEL_DWIDTH_CS7
  `undef MODEL_DWIDTH_CS7
`endif

`ifdef MODEL_SIZE_CS0
  `undef MODEL_SIZE_CS0
`endif

`ifdef MODEL_SIZE_CS1
  `undef MODEL_SIZE_CS1
`endif

`ifdef MODEL_SIZE_CS2
  `undef MODEL_SIZE_CS2
`endif

`ifdef MODEL_SIZE_CS3
  `undef MODEL_SIZE_CS3
`endif

`ifdef MODEL_SIZE_CS4
  `undef MODEL_SIZE_CS4
`endif

`ifdef MODEL_SIZE_CS5
  `undef MODEL_SIZE_CS5
`endif

`ifdef MODEL_SIZE_CS6
  `undef MODEL_SIZE_CS6
`endif

`ifdef MODEL_SIZE_CS7
  `undef MODEL_SIZE_CS7
`endif

`ifdef N_CS
  `undef N_CS
`endif

`ifdef NUM_DQS
  `undef NUM_DQS
`endif

`ifdef NUM_INIT_REF
  `undef NUM_INIT_REF
`endif

`ifdef OPEN_BANKS
  `undef OPEN_BANKS
`endif

`ifdef OP_IDLE_DSDC
  `undef OP_IDLE_DSDC
`endif

`ifdef OP_IDLE_SDC
  `undef OP_IDLE_SDC
`endif

`ifdef OP_WAIT_DSDC
  `undef OP_WAIT_DSDC
`endif

`ifdef OP_WAIT_SDC
  `undef OP_WAIT_SDC
`endif

`ifdef PAGE_MODE_SET0
  `undef PAGE_MODE_SET0
`endif

`ifdef PAGE_MODE_SET1
  `undef PAGE_MODE_SET1
`endif

`ifdef PAGE_MODE_SET2
  `undef PAGE_MODE_SET2
`endif

`ifdef PAGE_SIZE_SET0
  `undef PAGE_SIZE_SET0
`endif

`ifdef PAGE_SIZE_SET1
  `undef PAGE_SIZE_SET1
`endif

`ifdef PAGE_SIZE_SET2
  `undef PAGE_SIZE_SET2
`endif

`ifdef PD_REF_DSDC
  `undef PD_REF_DSDC
`endif

`ifdef PD_REF_SDC
  `undef PD_REF_SDC
`endif

`ifdef PD_RF_EXIT_DSDC
  `undef PD_RF_EXIT_DSDC
`endif

`ifdef PD_RF_EXIT_SDC
  `undef PD_RF_EXIT_SDC
`endif

`ifdef PIPE_ADDRESS_DECODER
  `undef PIPE_ADDRESS_DECODER
`endif

`ifdef POWER_DOWN
  `undef POWER_DOWN
`endif

`ifdef POWER_DOWN_DSDC
  `undef POWER_DOWN_DSDC
`endif

`ifdef POWER_DOWN_SDC
  `undef POWER_DOWN_SDC
`endif

`ifdef PREC_DSDC
  `undef PREC_DSDC
`endif

`ifdef PREC_SDC
  `undef PREC_SDC
`endif

`ifdef R_DATA
  `undef R_DATA
`endif

`ifdef R_DATA_DSDC
  `undef R_DATA_DSDC
`endif

`ifdef R_DATA_SDC
  `undef R_DATA_SDC
`endif

`ifdef RDY_READ_SMC
  `undef RDY_READ_SMC
`endif

`ifdef RDY_R_POP_SMC
  `undef RDY_R_POP_SMC
`endif

`ifdef RDY_R_WAIT_SMC
  `undef RDY_R_WAIT_SMC
`endif

`ifdef RDY_W_AS_SMC
  `undef RDY_W_AS_SMC
`endif

`ifdef RDY_W_WAIT_SMC
  `undef RDY_W_WAIT_SMC
`endif

`ifdef RDY_W_WE_SMC
  `undef RDY_W_WE_SMC
`endif

`ifdef READ
  `undef READ
`endif

`ifdef READ_DSDC
  `undef READ_DSDC
`endif

`ifdef READ_PIPE
  `undef READ_PIPE
`endif

`ifdef READ_SDC
  `undef READ_SDC
`endif

`ifdef READ_SMC
  `undef READ_SMC
`endif

`ifdef READY_MODE_SET0
  `undef READY_MODE_SET0
`endif

`ifdef READY_MODE_SET1
  `undef READY_MODE_SET1
`endif

`ifdef READY_MODE_SET2
  `undef READY_MODE_SET2
`endif

`ifdef REG_SELECT0
  `undef REG_SELECT0
`endif

`ifdef REG_SELECT1
  `undef REG_SELECT1
`endif

`ifdef REG_SELECT2
  `undef REG_SELECT2
`endif

`ifdef REG_SELECT3
  `undef REG_SELECT3
`endif

`ifdef REG_SELECT4
  `undef REG_SELECT4
`endif

`ifdef REG_SELECT5
  `undef REG_SELECT5
`endif

`ifdef REG_SELECT6
  `undef REG_SELECT6
`endif

`ifdef REG_SELECT7
  `undef REG_SELECT7
`endif

`ifdef RM_BCM01
  `undef RM_BCM01
`endif

`ifdef RM_BCM02
  `undef RM_BCM02
`endif

`ifdef RM_BCM03
  `undef RM_BCM03
`endif

`ifdef RM_BCM05
  `undef RM_BCM05
`endif

`ifdef RM_BCM06
  `undef RM_BCM06
`endif

`ifdef RM_BCM07
  `undef RM_BCM07
`endif

`ifdef RM_BCM08
  `undef RM_BCM08
`endif

`ifdef RM_BCM09
  `undef RM_BCM09
`endif

`ifdef RM_BCM10
  `undef RM_BCM10
`endif

`ifdef RM_BCM11
  `undef RM_BCM11
`endif

`ifdef RM_BCM12
  `undef RM_BCM12
`endif

`ifdef RM_BCM15
  `undef RM_BCM15
`endif

`ifdef RM_BCM16
  `undef RM_BCM16
`endif

`ifdef RM_BCM21
  `undef RM_BCM21
`endif

`ifdef RM_BCM22
  `undef RM_BCM22
`endif

`ifdef RM_BCM23
  `undef RM_BCM23
`endif

`ifdef RM_BCM24
  `undef RM_BCM24
`endif

`ifdef RM_BCM25
  `undef RM_BCM25
`endif

`ifdef RM_BCM26
  `undef RM_BCM26
`endif

`ifdef RM_BCM27
  `undef RM_BCM27
`endif

`ifdef RM_BCM28
  `undef RM_BCM28
`endif

`ifdef RM_BCM29
  `undef RM_BCM29
`endif

`ifdef RM_BCM30
  `undef RM_BCM30
`endif

`ifdef RM_BCM31
  `undef RM_BCM31
`endif

`ifdef RM_BCM32
  `undef RM_BCM32
`endif

`ifdef RM_BCM43
  `undef RM_BCM43
`endif

`ifdef RM_BCM44
  `undef RM_BCM44
`endif

`ifdef RM_BCM46_A
  `undef RM_BCM46_A
`endif

`ifdef RM_BCM46_B
  `undef RM_BCM46_B
`endif

`ifdef RM_BCM46_C
  `undef RM_BCM46_C
`endif

`ifdef RM_BCM46_D
  `undef RM_BCM46_D
`endif

`ifdef RM_BCM47
  `undef RM_BCM47
`endif

`ifdef RM_BCM51
  `undef RM_BCM51
`endif

`ifdef RM_BCM52
  `undef RM_BCM52
`endif

`ifdef RM_BCM53
  `undef RM_BCM53
`endif

`ifdef RM_BCM54
  `undef RM_BCM54
`endif

`ifdef RM_BCM55
  `undef RM_BCM55
`endif

`ifdef RM_BCM57
  `undef RM_BCM57
`endif

`ifdef RM_BCM58
  `undef RM_BCM58
`endif

`ifdef RM_BCM59
  `undef RM_BCM59
`endif

`ifdef RM_BCM64
  `undef RM_BCM64
`endif

`ifdef RM_BCM65
  `undef RM_BCM65
`endif

`ifdef RM_BCM66
  `undef RM_BCM66
`endif

`ifdef RM_BCM71
  `undef RM_BCM71
`endif

`ifdef RM_BCM72
  `undef RM_BCM72
`endif

`ifdef RM_BCM73
  `undef RM_BCM73
`endif

`ifdef RM_BCM76
  `undef RM_BCM76
`endif

`ifdef R_PREC_DSDC
  `undef R_PREC_DSDC
`endif

`ifdef R_PREC_SDC
  `undef R_PREC_SDC
`endif

`ifdef R_RAS_DSDC
  `undef R_RAS_DSDC
`endif

`ifdef R_RAS_SDC
  `undef R_RAS_SDC
`endif

`ifdef R_TERM
  `undef R_TERM
`endif

`ifdef R_TERM_DSDC
  `undef R_TERM_DSDC
`endif

`ifdef R_TERM_SDC
  `undef R_TERM_SDC
`endif

`ifdef R_TERM_SMC
  `undef R_TERM_SMC
`endif

`ifdef RW_IDLE_DSDC
  `undef RW_IDLE_DSDC
`endif

`ifdef RW_IDLE_SDC
  `undef RW_IDLE_SDC
`endif

`ifdef RW_IDLE_SMC
  `undef RW_IDLE_SMC
`endif

`ifdef S_BANK_ADDR_WIDTH
  `undef S_BANK_ADDR_WIDTH
`endif

`ifdef S_COL_ADDR_WIDTH
  `undef S_COL_ADDR_WIDTH
`endif

`ifdef SCONR_IN
  `undef SCONR_IN
`endif

`ifdef SCTLR_IN
  `undef SCTLR_IN
`endif

`ifdef S_DATA_WIDTH
  `undef S_DATA_WIDTH
`endif

`ifdef SD_GNT
  `undef SD_GNT
`endif

`ifdef SDRAM_SYNCFLASH
  `undef SDRAM_SYNCFLASH
`endif

`ifdef SELF_REF_DSDC
  `undef SELF_REF_DSDC
`endif

`ifdef SELF_REF_SDC
  `undef SELF_REF_SDC
`endif

`ifdef SF_BANK_ADDR_WIDTH
  `undef SF_BANK_ADDR_WIDTH
`endif

`ifdef SF_CAS_LATENCY
  `undef SF_CAS_LATENCY
`endif

`ifdef SF_COL_ADDR_WIDTH
  `undef SF_COL_ADDR_WIDTH
`endif

`ifdef SF_GNT
  `undef SF_GNT
`endif

`ifdef SF_T_RC
  `undef SF_T_RC
`endif

`ifdef SF_T_RCD
  `undef SF_T_RCD
`endif

`ifdef SMCR_16RD1
  `undef SMCR_16RD1
`endif

`ifdef SMCR_16RD2
  `undef SMCR_16RD2
`endif

`ifdef SMCR_16WR1
  `undef SMCR_16WR1
`endif

`ifdef SMCR_16WR2
  `undef SMCR_16WR2
`endif

`ifdef SMCR_DONE
  `undef SMCR_DONE
`endif

`ifdef SMCR_IDLE
  `undef SMCR_IDLE
`endif

`ifdef SMCR_WR_DONE
  `undef SMCR_WR_DONE
`endif

`ifdef SMCTLR_IN
  `undef SMCTLR_IN
`endif

`ifdef SM_DATA_WIDTH_SET0
  `undef SM_DATA_WIDTH_SET0
`endif

`ifdef SM_DATA_WIDTH_SET1
  `undef SM_DATA_WIDTH_SET1
`endif

`ifdef SM_DATA_WIDTH_SET2
  `undef SM_DATA_WIDTH_SET2
`endif

`ifdef SM_IDLE_SMC
  `undef SM_IDLE_SMC
`endif

`ifdef SM_READ_PIPE_SET0
  `undef SM_READ_PIPE_SET0
`endif

`ifdef SM_READ_PIPE_SET1
  `undef SM_READ_PIPE_SET1
`endif

`ifdef SM_READ_PIPE_SET2
  `undef SM_READ_PIPE_SET2
`endif

`ifdef SMSKR0_IN
  `undef SMSKR0_IN
`endif

`ifdef SMSKR1_IN
  `undef SMSKR1_IN
`endif

`ifdef SMSKR2_IN
  `undef SMSKR2_IN
`endif

`ifdef SMSKR3_IN
  `undef SMSKR3_IN
`endif

`ifdef SMSKR4_IN
  `undef SMSKR4_IN
`endif

`ifdef SMSKR5_IN
  `undef SMSKR5_IN
`endif

`ifdef SMSKR6_IN
  `undef SMSKR6_IN
`endif

`ifdef SMSKR7_IN
  `undef SMSKR7_IN
`endif

`ifdef SMTMGR_SET0_IN
  `undef SMTMGR_SET0_IN
`endif

`ifdef SMTMGR_SET1_IN
  `undef SMTMGR_SET1_IN
`endif

`ifdef SMTMGR_SET2_IN
  `undef SMTMGR_SET2_IN
`endif

`ifdef SM_WRITE_PIPE
  `undef SM_WRITE_PIPE
`endif

`ifdef S_RD_DATA_WIDTH
  `undef S_RD_DATA_WIDTH
`endif

`ifdef S_READY_VALID
  `undef S_READY_VALID
`endif

`ifdef SREFR_IN
  `undef SREFR_IN
`endif

`ifdef SR_EN_RF_DSDC
  `undef SR_EN_RF_DSDC
`endif

`ifdef SR_EN_RF_SDC
  `undef SR_EN_RF_SDC
`endif

`ifdef SR_EXIT_DSDC
  `undef SR_EXIT_DSDC
`endif

`ifdef SR_EXIT_SDC
  `undef SR_EXIT_SDC
`endif

`ifdef SR_EX_RF_DSDC
  `undef SR_EX_RF_DSDC
`endif

`ifdef SR_EX_RF_SDC
  `undef SR_EX_RF_SDC
`endif

`ifdef STMG0R_IN
  `undef STMG0R_IN
`endif

`ifdef STMG1R_IN
  `undef STMG1R_IN
`endif

`ifdef T_AS_SET0
  `undef T_AS_SET0
`endif

`ifdef T_AS_SET1
  `undef T_AS_SET1
`endif

`ifdef T_AS_SET2
  `undef T_AS_SET2
`endif

`ifdef T_BTA_SET0
  `undef T_BTA_SET0
`endif

`ifdef T_BTA_SET1
  `undef T_BTA_SET1
`endif

`ifdef T_BTA_SET2
  `undef T_BTA_SET2
`endif

`ifdef T_INIT
  `undef T_INIT
`endif

`ifdef T_MRD
  `undef T_MRD
`endif

`ifdef T_MRD_DSDC
  `undef T_MRD_DSDC
`endif

`ifdef T_MRD_SDC
  `undef T_MRD_SDC
`endif

`ifdef T_PRC_SET0
  `undef T_PRC_SET0
`endif

`ifdef T_PRC_SET1
  `undef T_PRC_SET1
`endif

`ifdef T_PRC_SET2
  `undef T_PRC_SET2
`endif

`ifdef T_RAS_MIN
  `undef T_RAS_MIN
`endif

`ifdef T_RC
  `undef T_RC
`endif

`ifdef T_RCAR
  `undef T_RCAR
`endif

`ifdef T_RCD
  `undef T_RCD
`endif

`ifdef T_RC_SET0
  `undef T_RC_SET0
`endif

`ifdef T_RC_SET1
  `undef T_RC_SET1
`endif

`ifdef T_RC_SET2
  `undef T_RC_SET2
`endif

`ifdef T_REF
  `undef T_REF
`endif

`ifdef T_RP
  `undef T_RP
`endif

`ifdef T_RPD
  `undef T_RPD
`endif

`ifdef TWO_TO_ONE
  `undef TWO_TO_ONE
`endif

`ifdef T_WP_SET0
  `undef T_WP_SET0
`endif

`ifdef T_WP_SET1
  `undef T_WP_SET1
`endif

`ifdef T_WP_SET2
  `undef T_WP_SET2
`endif

`ifdef T_WR
  `undef T_WR
`endif

`ifdef T_WR_SET0
  `undef T_WR_SET0
`endif

`ifdef T_WR_SET1
  `undef T_WR_SET1
`endif

`ifdef T_WR_SET2
  `undef T_WR_SET2
`endif

`ifdef T_WTR
  `undef T_WTR
`endif

`ifdef T_XSR
  `undef T_XSR
`endif

`ifdef USE_FOUNDATION
  `undef USE_FOUNDATION
`endif

`ifdef USE_MOBILE_DDR
  `undef USE_MOBILE_DDR
`endif

`ifdef USE_SIDEBAND_SAMPLE
  `undef USE_SIDEBAND_SAMPLE
`endif

`ifdef VER_1_2A_COMPATIABLE_MODE
  `undef VER_1_2A_COMPATIABLE_MODE
`endif

`ifdef WAIT
  `undef WAIT
`endif

`ifdef WAIT_DSDC
  `undef WAIT_DSDC
`endif

`ifdef WAIT_SDC
  `undef WAIT_SDC
`endif

`ifdef W_AS_SMC
  `undef W_AS_SMC
`endif

`ifdef W_POP_DSDC
  `undef W_POP_DSDC
`endif

`ifdef W_POP_SDC
  `undef W_POP_SDC
`endif

`ifdef W_POP_SMC
  `undef W_POP_SMC
`endif

`ifdef W_PREC_DSDC
  `undef W_PREC_DSDC
`endif

`ifdef W_PREC_SDC
  `undef W_PREC_SDC
`endif

`ifdef WRD_CNT
  `undef WRD_CNT
`endif

`ifdef W_RF_WR_DSDC
  `undef W_RF_WR_DSDC
`endif

`ifdef W_RF_WR_SDC
  `undef W_RF_WR_SDC
`endif

`ifdef WRITE_DSDC
  `undef WRITE_DSDC
`endif

`ifdef WRITE_FIFO_DEPTH
  `undef WRITE_FIFO_DEPTH
`endif

`ifdef WRITE_PIPE
  `undef WRITE_PIPE
`endif

`ifdef WRITE_SDC
  `undef WRITE_SDC
`endif

`ifdef W_SYNC_SMC
  `undef W_SYNC_SMC
`endif

`ifdef W_WE_SMC
  `undef W_WE_SMC
`endif

`ifdef W_WR_RAS_DSDC
  `undef W_WR_RAS_DSDC
`endif

`ifdef W_WR_RAS_SDC
  `undef W_WR_RAS_SDC
`endif

`ifdef W_WR_SMC
  `undef W_WR_SMC
`endif

