
   `undef USE_FOUNDATION
   `undef X2H_AXI_ADDR_WIDTH
   `undef X2H_AXI_DATA_WIDTH
   `undef X2H_AXI_ID_WIDTH
   `undef X2H_LOWPWR_HS_IF
   `undef X2H_LOWPWR_NOPX_CNT
   `undef X2H_LOWPWR_NOPX_CNT_W
   `undef X2H_LOWPWR_LEGACY_IF
   `undef X2H_AXI_LOW_POWER
   `undef X2H_MAX_PENDTRANS_READ
   `undef X2H_MAX_PENDTRANS_WRITE
   `undef X2H_CNT_PENDTRANS_READ_W
   `undef X2H_CNT_PENDTRANS_WRITE_W
   `undef X2H_WRITE_DATA_INTERLEAVING_DEPTH
   `undef X2H_EXCLUSIVE_ACCESS_DEPTH
   `undef X2H_AXI_ENDIANNESS
   `undef X2H_CLK_MODE
   `undef X2H_CMD_QUEUE_DEPTH
   `undef X2H_WRITE_BUFFER_DEPTH
   `undef X2H_WRITE_RESP_BUFFER_DEPTH
   `undef X2H_READ_BUFFER_DEPTH
   `undef X2H_AHB_ADDR_WIDTH
   `undef X2H_AHB_DATA_WIDTH
   `undef X2H_AHB_LITE
   `undef X2H_PASS_LOCK
   `undef X2H_USE_DEFINED_ONLY
   `undef X2H_AHB_BUFFER_POP_MODE
   `undef X2H_AHB_ENDIANNESS
   `undef SIM_A_CLK_PERIOD
   `undef SIM_B_CLK_PERIOD
   `undef SIM_NUM_SEQUENCES
   `undef SIM_DEBUG_LEVEL
   `undef SIM_USE_VARIABLE_SEED
   `undef SIM_B_DEF_MASTER
   `undef SIM_A_TTICK_CLK_CYCLES
   `undef SIM_B_TTICK_CLK_CYCLES
   `undef SIM_A_START_ADDR_S1
   `undef SIM_A_END_ADDR_S1
   `undef SIM_A_START_ADDR_S2
   `undef SIM_A_END_ADDR_S2
   `undef SIM_A_START_ADDR_S3
   `undef SIM_A_END_ADDR_S3
   `undef SIM_B_START_ADDR_S1
   `undef SIM_B_END_ADDR_S1
   `undef SIM_B_START_ADDR_S3
   `undef SIM_B_END_ADDR_S3
   `undef SIM_B_START_ADDR_S2
   `undef SIM_B_END_ADDR_S2
   `undef X2H_SYNC_MODE
   `undef AXI_TEST_RAND_XACTNS
   `undef AXI_TEST_INACTIVE_SIGNALS
   `undef X2H_AHB_HTRANS_IDLE
   `undef X2H_AHB_HTRANS_BUSY
   `undef X2H_AHB_HTRANS_NONSEQ
   `undef X2H_AHB_HTRANS_SEQ
   `undef X2H_AHB_HBURST_SINGLE
   `undef X2H_AHB_HBURST_INCR
   `undef X2H_AHB_HBURST_WRAP4
   `undef X2H_AHB_HBURST_INCR4
   `undef X2H_AHB_HBURST_WRAP8
   `undef X2H_AHB_HBURST_INCR8
   `undef X2H_AHB_HBURST_WRAP16
   `undef X2H_AHB_HBURST_INCR16
   `undef X2H_AMBA_SIZE_1BYTE
   `undef X2H_AMBA_SIZE_2BYTE
   `undef X2H_AMBA_SIZE_4BYTE
   `undef X2H_AMBA_SIZE_8BYTE
   `undef X2H_AMBA_SIZE_16BYTE
   `undef X2H_AMBA_SIZE_32BYTE
   `undef X2H_AMBA_SIZE_64BYTE
   `undef X2H_AXI_BURST_FIXED
   `undef X2H_AXI_BURST_INCR
   `undef X2H_AXI_BURST_WRAP
   `undef X2H_AXI_BURST_RESERVED
   `undef X2H_AXI_RESP_OKAY
   `undef X2H_AXI_RESP_EXOKAY
   `undef X2H_AXI_RESP_SLVERR
   `undef X2H_AXI_RESP_DECERR
   `undef X2H_AHB_RESP_OKAY
   `undef X2H_AHB_RESP_ERROR
   `undef X2H_AHB_RESP_RETRY
   `undef X2H_AHB_RESP_SPLIT
   `undef X2H_AXI_WSTRB_WIDTH
   `undef X2H_AHB_WSTRB_WIDTH
   `undef X2H_AXI_WDFIFO_WIDTH
   `undef X2H_CMD_ADDR_WIDTH
   `undef X2H_CMD_QUEUE_WIDTH
   `undef RM_BCM05
   `undef RM_BCM06
   `undef RM_BCM07
   `undef RM_BCM21
   `undef RM_BCM57
   `undef DW_cont_msb
`define cb_dummy_parameter_definition 1
`undef  cb_dummy_parameter_definition
