// This file was automatically generated by coreAssembler (version G-2012.06-SP1-1).
// 
// FILENAME : /home/hll/HLL/PAS_sdram_if/axi/src/axi.v
// DATE : 08/04/15 16:16:24
// ABSTRACT : Verilog top-level subsystem RTL.
// 

module axi (// Ports for Interface ACLK
            ACLK_aclk,
            // Ports for Interface ARESETn
            ARESETn_aresetn,
            // Ports for Interface HCLK
            HCLK_hclk,
            // Ports for Interface HRESETn
            HRESETn_hresetn,
            // Ports for Interface gen_m_rd
            gen_m_rd_maddr,
            gen_m_rd_mburst,
            gen_m_rd_mcache,
            gen_m_rd_mdata,
            gen_m_rd_mid,
            gen_m_rd_mlen,
            gen_m_rd_mlock,
            gen_m_rd_mprot,
            gen_m_rd_mread,
            gen_m_rd_mready,
            gen_m_rd_msize,
            gen_m_rd_mwrite,
            gen_m_rd_mwstrb,
            gen_m_rd_saccept,
            gen_m_rd_sdata,
            gen_m_rd_sid,
            gen_m_rd_slast,
            gen_m_rd_sresp,
            gen_m_rd_svalid,
            // Ports for Interface gen_m_wr
            gen_m_wr_maddr,
            gen_m_wr_mburst,
            gen_m_wr_mcache,
            gen_m_wr_mdata,
            gen_m_wr_mid,
            gen_m_wr_mlen,
            gen_m_wr_mlock,
            gen_m_wr_mprot,
            gen_m_wr_mread,
            gen_m_wr_mready,
            gen_m_wr_msize,
            gen_m_wr_mwrite,
            gen_m_wr_mwstrb,
            gen_m_wr_saccept,
            gen_m_wr_sdata,
            gen_m_wr_sid,
            gen_m_wr_slast,
            gen_m_wr_sresp,
            gen_m_wr_svalid,
            // Ports for Manually exported pins
            gm_rd_gclken,
            gm_wr_gclken,
            i_axi_remap_n,
            i_memctl_clear_sr_dp,
            i_memctl_gpi,
            i_memctl_power_down,
            i_memctl_remap,
            i_memctl_s_rd_data,
            i_memctl_s_rd_ready,
            i_memctl_s_sda_in,
            i_ahb_hmaster_data,
            i_axi_dbg_araddr_s0,
            i_axi_dbg_arburst_s0,
            i_axi_dbg_arcache_s0,
            i_axi_dbg_arid_s0,
            i_axi_dbg_arlen_s0,
            i_axi_dbg_arlock_s0,
            i_axi_dbg_arprot_s0,
            i_axi_dbg_arready_s0,
            i_axi_dbg_arsize_s0,
            i_axi_dbg_arvalid_s0,
            i_axi_dbg_awaddr_s0,
            i_axi_dbg_awburst_s0,
            i_axi_dbg_awcache_s0,
            i_axi_dbg_awid_s0,
            i_axi_dbg_awlen_s0,
            i_axi_dbg_awlock_s0,
            i_axi_dbg_awprot_s0,
            i_axi_dbg_awready_s0,
            i_axi_dbg_awsize_s0,
            i_axi_dbg_awvalid_s0,
            i_axi_dbg_bid_s0,
            i_axi_dbg_bready_s0,
            i_axi_dbg_bresp_s0,
            i_axi_dbg_bvalid_s0,
            i_axi_dbg_rdata_s0,
            i_axi_dbg_rid_s0,
            i_axi_dbg_rlast_s0,
            i_axi_dbg_rready_s0,
            i_axi_dbg_rresp_s0,
            i_axi_dbg_rvalid_s0,
            i_axi_dbg_wdata_s0,
            i_axi_dbg_wid_s0,
            i_axi_dbg_wlast_s0,
            i_axi_dbg_wready_s0,
            i_axi_dbg_wstrb_s0,
            i_axi_dbg_wvalid_s0,
            i_axi_x2h_cactive,
            i_memctl_debug_ad_bank_addr,
            i_memctl_debug_ad_col_addr,
            i_memctl_debug_ad_row_addr,
            i_memctl_debug_ad_sf_bank_addr,
            i_memctl_debug_ad_sf_col_addr,
            i_memctl_debug_ad_sf_row_addr,
            i_memctl_debug_hiu_addr,
            i_memctl_debug_ref_req,
            i_memctl_debug_sm_burst_done,
            i_memctl_debug_sm_pop_n,
            i_memctl_debug_sm_push_n,
            i_memctl_debug_smc_cs,
            i_memctl_gpo,
            i_memctl_s_addr,
            i_memctl_s_bank_addr,
            i_memctl_s_cas_latency,
            i_memctl_s_cas_n,
            i_memctl_s_cke,
            i_memctl_s_dout_valid,
            i_memctl_s_dqm,
            i_memctl_s_ras_n,
            i_memctl_s_rd_dqs_mask,
            i_memctl_s_rd_end,
            i_memctl_s_rd_pop,
            i_memctl_s_rd_start,
            i_memctl_s_read_pipe,
            i_memctl_s_sa,
            i_memctl_s_scl,
            i_memctl_s_sda_oe_n,
            i_memctl_s_sda_out,
            i_memctl_s_sel_n,
            i_memctl_s_we_n,
            i_memctl_s_wr_data
            );

   // Ports for Interface ACLK
   input          ACLK_aclk;
   // Ports for Interface ARESETn
   input          ARESETn_aresetn;
   // Ports for Interface HCLK
   input          HCLK_hclk;
   // Ports for Interface HRESETn
   input          HRESETn_hresetn;
   // Ports for Interface gen_m_rd
   input  [31:0]  gen_m_rd_maddr;
   input  [1:0]   gen_m_rd_mburst;
   input  [3:0]   gen_m_rd_mcache;
   input  [63:0]  gen_m_rd_mdata;
   input  [3:0]   gen_m_rd_mid;
   input  [3:0]   gen_m_rd_mlen;
   input          gen_m_rd_mlock;
   input  [2:0]   gen_m_rd_mprot;
   input          gen_m_rd_mread;
   input          gen_m_rd_mready;
   input  [2:0]   gen_m_rd_msize;
   input          gen_m_rd_mwrite;
   input  [7:0]   gen_m_rd_mwstrb;
   output         gen_m_rd_saccept;
   output [63:0]  gen_m_rd_sdata;
   output [3:0]   gen_m_rd_sid;
   output         gen_m_rd_slast;
   output [2:0]   gen_m_rd_sresp;
   output         gen_m_rd_svalid;
   // Ports for Interface gen_m_wr
   input  [31:0]  gen_m_wr_maddr;
   input  [1:0]   gen_m_wr_mburst;
   input  [3:0]   gen_m_wr_mcache;
   input  [63:0]  gen_m_wr_mdata;
   input  [3:0]   gen_m_wr_mid;
   input  [3:0]   gen_m_wr_mlen;
   input          gen_m_wr_mlock;
   input  [2:0]   gen_m_wr_mprot;
   input          gen_m_wr_mread;
   input          gen_m_wr_mready;
   input  [2:0]   gen_m_wr_msize;
   input          gen_m_wr_mwrite;
   input  [7:0]   gen_m_wr_mwstrb;
   output         gen_m_wr_saccept;
   output [63:0]  gen_m_wr_sdata;
   output [3:0]   gen_m_wr_sid;
   output         gen_m_wr_slast;
   output [2:0]   gen_m_wr_sresp;
   output         gen_m_wr_svalid;
   // Ports for Manually exported pins
   input          gm_rd_gclken;
   input          gm_wr_gclken;
   input          i_axi_remap_n;
   input          i_memctl_clear_sr_dp;
   input  [7:0]   i_memctl_gpi;
   input          i_memctl_power_down;
   input          i_memctl_remap;
   input  [31:0]  i_memctl_s_rd_data;
   input          i_memctl_s_rd_ready;
   input          i_memctl_s_sda_in;
   output [3:0]   i_ahb_hmaster_data;
   output [31:0]  i_axi_dbg_araddr_s0;
   output [1:0]   i_axi_dbg_arburst_s0;
   output [3:0]   i_axi_dbg_arcache_s0;
   output [4:0]   i_axi_dbg_arid_s0;
   output [3:0]   i_axi_dbg_arlen_s0;
   output [1:0]   i_axi_dbg_arlock_s0;
   output [2:0]   i_axi_dbg_arprot_s0;
   output         i_axi_dbg_arready_s0;
   output [2:0]   i_axi_dbg_arsize_s0;
   output         i_axi_dbg_arvalid_s0;
   output [31:0]  i_axi_dbg_awaddr_s0;
   output [1:0]   i_axi_dbg_awburst_s0;
   output [3:0]   i_axi_dbg_awcache_s0;
   output [4:0]   i_axi_dbg_awid_s0;
   output [3:0]   i_axi_dbg_awlen_s0;
   output [1:0]   i_axi_dbg_awlock_s0;
   output [2:0]   i_axi_dbg_awprot_s0;
   output         i_axi_dbg_awready_s0;
   output [2:0]   i_axi_dbg_awsize_s0;
   output         i_axi_dbg_awvalid_s0;
   output [4:0]   i_axi_dbg_bid_s0;
   output         i_axi_dbg_bready_s0;
   output [1:0]   i_axi_dbg_bresp_s0;
   output         i_axi_dbg_bvalid_s0;
   output [63:0]  i_axi_dbg_rdata_s0;
   output [4:0]   i_axi_dbg_rid_s0;
   output         i_axi_dbg_rlast_s0;
   output         i_axi_dbg_rready_s0;
   output [1:0]   i_axi_dbg_rresp_s0;
   output         i_axi_dbg_rvalid_s0;
   output [63:0]  i_axi_dbg_wdata_s0;
   output [4:0]   i_axi_dbg_wid_s0;
   output         i_axi_dbg_wlast_s0;
   output         i_axi_dbg_wready_s0;
   output [7:0]   i_axi_dbg_wstrb_s0;
   output         i_axi_dbg_wvalid_s0;
   output         i_axi_x2h_cactive;
   output [1:0]   i_memctl_debug_ad_bank_addr;
   output [12:0]  i_memctl_debug_ad_col_addr;
   output [12:0]  i_memctl_debug_ad_row_addr;
   output [1:0]   i_memctl_debug_ad_sf_bank_addr;
   output [12:0]  i_memctl_debug_ad_sf_col_addr;
   output [12:0]  i_memctl_debug_ad_sf_row_addr;
   output [31:0]  i_memctl_debug_hiu_addr;
   output         i_memctl_debug_ref_req;
   output         i_memctl_debug_sm_burst_done;
   output         i_memctl_debug_sm_pop_n;
   output         i_memctl_debug_sm_push_n;
   output [3:0]   i_memctl_debug_smc_cs;
   output [7:0]   i_memctl_gpo;
   output [12:0]  i_memctl_s_addr;
   output [1:0]   i_memctl_s_bank_addr;
   output [2:0]   i_memctl_s_cas_latency;
   output         i_memctl_s_cas_n;
   output         i_memctl_s_cke;
   output [3:0]   i_memctl_s_dout_valid;
   output [3:0]   i_memctl_s_dqm;
   output         i_memctl_s_ras_n;
   output         i_memctl_s_rd_dqs_mask;
   output         i_memctl_s_rd_end;
   output         i_memctl_s_rd_pop;
   output         i_memctl_s_rd_start;
   output [2:0]   i_memctl_s_read_pipe;
   output [2:0]   i_memctl_s_sa;
   output         i_memctl_s_scl;
   output         i_memctl_s_sda_oe_n;
   output         i_memctl_s_sda_out;
   output         i_memctl_s_sel_n;
   output         i_memctl_s_we_n;
   output [31:0]  i_memctl_s_wr_data;

   wire [31:0]  gm_rd_araddr;
   wire [1:0]   gm_rd_arburst;
   wire [3:0]   gm_rd_arcache;
   wire [3:0]   gm_rd_arid;
   wire [3:0]   gm_rd_arlen;
   wire [1:0]   gm_rd_arlock;
   wire [2:0]   gm_rd_arprot;
   wire [2:0]   gm_rd_arsize;
   wire         gm_rd_arvalid;
   wire [31:0]  gm_rd_awaddr;
   wire [1:0]   gm_rd_awburst;
   wire [3:0]   gm_rd_awcache;
   wire [3:0]   gm_rd_awid;
   wire [3:0]   gm_rd_awlen;
   wire [1:0]   gm_rd_awlock;
   wire [2:0]   gm_rd_awprot;
   wire [2:0]   gm_rd_awsize;
   wire         gm_rd_awvalid;
   wire         gm_rd_bready;
   wire         gm_rd_rready;
   wire [63:0]  gm_rd_wdata;
   wire [3:0]   gm_rd_wid;
   wire         gm_rd_wlast;
   wire [7:0]   gm_rd_wstrb;
   wire         gm_rd_wvalid;
   wire [31:0]  gm_wr_araddr;
   wire [1:0]   gm_wr_arburst;
   wire [3:0]   gm_wr_arcache;
   wire [3:0]   gm_wr_arid;
   wire [3:0]   gm_wr_arlen;
   wire [1:0]   gm_wr_arlock;
   wire [2:0]   gm_wr_arprot;
   wire [2:0]   gm_wr_arsize;
   wire         gm_wr_arvalid;
   wire [31:0]  gm_wr_awaddr;
   wire [1:0]   gm_wr_awburst;
   wire [3:0]   gm_wr_awcache;
   wire [3:0]   gm_wr_awid;
   wire [3:0]   gm_wr_awlen;
   wire [1:0]   gm_wr_awlock;
   wire [2:0]   gm_wr_awprot;
   wire [2:0]   gm_wr_awsize;
   wire         gm_wr_awvalid;
   wire         gm_wr_bready;
   wire         gm_wr_rready;
   wire [63:0]  gm_wr_wdata;
   wire [3:0]   gm_wr_wid;
   wire         gm_wr_wlast;
   wire [7:0]   gm_wr_wstrb;
   wire         gm_wr_wvalid;
   wire [31:0]  i_ahb_haddr;
   wire [2:0]   i_ahb_hburst;
   wire         i_ahb_hgrant_m1;
   wire [31:0]  i_ahb_hrdata;
   wire         i_ahb_hready;
   wire [1:0]   i_ahb_hresp;
   wire         i_ahb_hsel_s1;
   wire         i_ahb_hsel_s2;
   wire [2:0]   i_ahb_hsize;
   wire [1:0]   i_ahb_htrans;
   wire [31:0]  i_ahb_hwdata;
   wire         i_ahb_hwrite;
   wire [31:0]  i_axi_araddr_s1;
   wire [1:0]   i_axi_arburst_s1;
   wire [3:0]   i_axi_arcache_s1;
   wire [4:0]   i_axi_arid_s1;
   wire [3:0]   i_axi_arlen_s1;
   wire [1:0]   i_axi_arlock_s1;
   wire [2:0]   i_axi_arprot_s1;
   wire         i_axi_arready_m1;
   wire         i_axi_arready_m2;
   wire [2:0]   i_axi_arsize_s1;
   wire         i_axi_arvalid_s1;
   wire [31:0]  i_axi_awaddr_s1;
   wire [1:0]   i_axi_awburst_s1;
   wire [3:0]   i_axi_awcache_s1;
   wire [4:0]   i_axi_awid_s1;
   wire [3:0]   i_axi_awlen_s1;
   wire [1:0]   i_axi_awlock_s1;
   wire [2:0]   i_axi_awprot_s1;
   wire         i_axi_awready_m1;
   wire         i_axi_awready_m2;
   wire [2:0]   i_axi_awsize_s1;
   wire         i_axi_awvalid_s1;
   wire [3:0]   i_axi_bid_m1;
   wire [3:0]   i_axi_bid_m2;
   wire         i_axi_bready_s1;
   wire [1:0]   i_axi_bresp_m1;
   wire [1:0]   i_axi_bresp_m2;
   wire         i_axi_bvalid_m1;
   wire         i_axi_bvalid_m2;
   wire [63:0]  i_axi_rdata_m1;
   wire [63:0]  i_axi_rdata_m2;
   wire [3:0]   i_axi_rid_m1;
   wire [3:0]   i_axi_rid_m2;
   wire         i_axi_rlast_m1;
   wire         i_axi_rlast_m2;
   wire         i_axi_rready_s1;
   wire [1:0]   i_axi_rresp_m1;
   wire [1:0]   i_axi_rresp_m2;
   wire         i_axi_rvalid_m1;
   wire         i_axi_rvalid_m2;
   wire [63:0]  i_axi_wdata_s1;
   wire [4:0]   i_axi_wid_s1;
   wire         i_axi_wlast_s1;
   wire         i_axi_wready_m1;
   wire         i_axi_wready_m2;
   wire [7:0]   i_axi_wstrb_s1;
   wire         i_axi_wvalid_s1;
   wire         i_axi_x2h_arready;
   wire         i_axi_x2h_awready;
   wire [4:0]   i_axi_x2h_bid;
   wire [1:0]   i_axi_x2h_bresp;
   wire         i_axi_x2h_bvalid;
   wire [31:0]  i_axi_x2h_mhaddr;
   wire [2:0]   i_axi_x2h_mhburst;
   wire         i_axi_x2h_mhbusreq;
   wire         i_axi_x2h_mhlock;
   wire [3:0]   i_axi_x2h_mhprot;
   wire [2:0]   i_axi_x2h_mhsize;
   wire [1:0]   i_axi_x2h_mhtrans;
   wire [31:0]  i_axi_x2h_mhwdata;
   wire         i_axi_x2h_mhwrite;
   wire [63:0]  i_axi_x2h_rdata;
   wire [4:0]   i_axi_x2h_rid;
   wire         i_axi_x2h_rlast;
   wire [1:0]   i_axi_x2h_rresp;
   wire         i_axi_x2h_rvalid;
   wire         i_axi_x2h_wready;
   wire [31:0]  i_memctl_hrdata;
   wire         i_memctl_hready_resp;
   wire [1:0]   i_memctl_hresp;

   gm_rd_DW_axi_gm gm_rd
      (.saccept (gen_m_rd_saccept),
       .sid     (gen_m_rd_sid),
       .svalid  (gen_m_rd_svalid),
       .slast   (gen_m_rd_slast),
       .sdata   (gen_m_rd_sdata),
       .sresp   (gen_m_rd_sresp),
       .awid    (gm_rd_awid),
       .awvalid (gm_rd_awvalid),
       .awaddr  (gm_rd_awaddr),
       .awlen   (gm_rd_awlen),
       .awsize  (gm_rd_awsize),
       .awburst (gm_rd_awburst),
       .awlock  (gm_rd_awlock),
       .awcache (gm_rd_awcache),
       .awprot  (gm_rd_awprot),
       .wid     (gm_rd_wid),
       .wvalid  (gm_rd_wvalid),
       .wlast   (gm_rd_wlast),
       .wdata   (gm_rd_wdata),
       .wstrb   (gm_rd_wstrb),
       .bready  (gm_rd_bready),
       .arid    (gm_rd_arid),
       .arvalid (gm_rd_arvalid),
       .araddr  (gm_rd_araddr),
       .arlen   (gm_rd_arlen),
       .arsize  (gm_rd_arsize),
       .arburst (gm_rd_arburst),
       .arlock  (gm_rd_arlock),
       .arcache (gm_rd_arcache),
       .arprot  (gm_rd_arprot),
       .rready  (gm_rd_rready),
       .aclk    (ACLK_aclk),
       .aresetn (ARESETn_aresetn),
       .gclken  (gm_rd_gclken),
       .mid     (gen_m_rd_mid),
       .maddr   (gen_m_rd_maddr),
       .mread   (gen_m_rd_mread),
       .mwrite  (gen_m_rd_mwrite),
       .mlock   (gen_m_rd_mlock),
       .mlen    (gen_m_rd_mlen),
       .msize   (gen_m_rd_msize),
       .mburst  (gen_m_rd_mburst),
       .mcache  (gen_m_rd_mcache),
       .mprot   (gen_m_rd_mprot),
       .mdata   (gen_m_rd_mdata),
       .mwstrb  (gen_m_rd_mwstrb),
       .mready  (gen_m_rd_mready),
       .awready (i_axi_awready_m2),
       .wready  (i_axi_wready_m2),
       .bid     (i_axi_bid_m2),
       .bvalid  (i_axi_bvalid_m2),
       .bresp   (i_axi_bresp_m2),
       .arready (i_axi_arready_m2),
       .rid     (i_axi_rid_m2),
       .rvalid  (i_axi_rvalid_m2),
       .rlast   (i_axi_rlast_m2),
       .rdata   (i_axi_rdata_m2),
       .rresp   (i_axi_rresp_m2));

   gm_wr_DW_axi_gm gm_wr
      (.saccept (gen_m_wr_saccept),
       .sid     (gen_m_wr_sid),
       .svalid  (gen_m_wr_svalid),
       .slast   (gen_m_wr_slast),
       .sdata   (gen_m_wr_sdata),
       .sresp   (gen_m_wr_sresp),
       .awid    (gm_wr_awid),
       .awvalid (gm_wr_awvalid),
       .awaddr  (gm_wr_awaddr),
       .awlen   (gm_wr_awlen),
       .awsize  (gm_wr_awsize),
       .awburst (gm_wr_awburst),
       .awlock  (gm_wr_awlock),
       .awcache (gm_wr_awcache),
       .awprot  (gm_wr_awprot),
       .wid     (gm_wr_wid),
       .wvalid  (gm_wr_wvalid),
       .wlast   (gm_wr_wlast),
       .wdata   (gm_wr_wdata),
       .wstrb   (gm_wr_wstrb),
       .bready  (gm_wr_bready),
       .arid    (gm_wr_arid),
       .arvalid (gm_wr_arvalid),
       .araddr  (gm_wr_araddr),
       .arlen   (gm_wr_arlen),
       .arsize  (gm_wr_arsize),
       .arburst (gm_wr_arburst),
       .arlock  (gm_wr_arlock),
       .arcache (gm_wr_arcache),
       .arprot  (gm_wr_arprot),
       .rready  (gm_wr_rready),
       .aclk    (ACLK_aclk),
       .aresetn (ARESETn_aresetn),
       .gclken  (gm_wr_gclken),
       .mid     (gen_m_wr_mid),
       .maddr   (gen_m_wr_maddr),
       .mread   (gen_m_wr_mread),
       .mwrite  (gen_m_wr_mwrite),
       .mlock   (gen_m_wr_mlock),
       .mlen    (gen_m_wr_mlen),
       .msize   (gen_m_wr_msize),
       .mburst  (gen_m_wr_mburst),
       .mcache  (gen_m_wr_mcache),
       .mprot   (gen_m_wr_mprot),
       .mdata   (gen_m_wr_mdata),
       .mwstrb  (gen_m_wr_mwstrb),
       .mready  (gen_m_wr_mready),
       .awready (i_axi_awready_m1),
       .wready  (i_axi_wready_m1),
       .bid     (i_axi_bid_m1),
       .bvalid  (i_axi_bvalid_m1),
       .bresp   (i_axi_bresp_m1),
       .arready (i_axi_arready_m1),
       .rid     (i_axi_rid_m1),
       .rvalid  (i_axi_rvalid_m1),
       .rlast   (i_axi_rlast_m1),
       .rdata   (i_axi_rdata_m1),
       .rresp   (i_axi_rresp_m1));

   i_ahb_DW_ahb i_ahb
      (.hclk           (HCLK_hclk),
       .hresetn        (HRESETn_hresetn),
       .haddr_m1       (i_axi_x2h_mhaddr),
       .hburst_m1      (i_axi_x2h_mhburst),
       .hbusreq_m1     (i_axi_x2h_mhbusreq),
       .hlock_m1       (i_axi_x2h_mhlock),
       .hprot_m1       (i_axi_x2h_mhprot),
       .hsize_m1       (i_axi_x2h_mhsize),
       .htrans_m1      (i_axi_x2h_mhtrans),
       .hwdata_m1      (i_axi_x2h_mhwdata),
       .hwrite_m1      (i_axi_x2h_mhwrite),
       .hgrant_m1      (i_ahb_hgrant_m1),
       .hsel_s1        (i_ahb_hsel_s1),
       .hready_resp_s1 (i_memctl_hready_resp),
       .hresp_s1       (i_memctl_hresp),
       .hrdata_s1      (i_memctl_hrdata),
       .hsel_s2        (i_ahb_hsel_s2),
       .haddr          (i_ahb_haddr),
       .hburst         (i_ahb_hburst),
       .hprot          (),
       .hsize          (i_ahb_hsize),
       .htrans         (i_ahb_htrans),
       .hwdata         (i_ahb_hwdata),
       .hwrite         (i_ahb_hwrite),
       .hready         (i_ahb_hready),
       .hresp          (i_ahb_hresp),
       .hrdata         (i_ahb_hrdata),
       .hmaster        (),
       .hmaster_data   (i_ahb_hmaster_data),
       .hmastlock      ());

   i_axi_DW_axi i_axi
      (.aclk           (ACLK_aclk),
       .aresetn        (ARESETn_aresetn),
       .awvalid_m1     (gm_wr_awvalid),
       .awaddr_m1      (gm_wr_awaddr),
       .awid_m1        (gm_wr_awid),
       .awlen_m1       (gm_wr_awlen),
       .awsize_m1      (gm_wr_awsize),
       .awburst_m1     (gm_wr_awburst),
       .awlock_m1      (gm_wr_awlock),
       .awcache_m1     (gm_wr_awcache),
       .awprot_m1      (gm_wr_awprot),
       .awready_m1     (i_axi_awready_m1),
       .wvalid_m1      (gm_wr_wvalid),
       .wid_m1         (gm_wr_wid),
       .wdata_m1       (gm_wr_wdata),
       .wstrb_m1       (gm_wr_wstrb),
       .wlast_m1       (gm_wr_wlast),
       .wready_m1      (i_axi_wready_m1),
       .bvalid_m1      (i_axi_bvalid_m1),
       .bid_m1         (i_axi_bid_m1),
       .bresp_m1       (i_axi_bresp_m1),
       .bready_m1      (gm_wr_bready),
       .arvalid_m1     (gm_wr_arvalid),
       .arid_m1        (gm_wr_arid),
       .araddr_m1      (gm_wr_araddr),
       .arlen_m1       (gm_wr_arlen),
       .arsize_m1      (gm_wr_arsize),
       .arburst_m1     (gm_wr_arburst),
       .arlock_m1      (gm_wr_arlock),
       .arcache_m1     (gm_wr_arcache),
       .arprot_m1      (gm_wr_arprot),
       .arready_m1     (i_axi_arready_m1),
       .rvalid_m1      (i_axi_rvalid_m1),
       .rid_m1         (i_axi_rid_m1),
       .rdata_m1       (i_axi_rdata_m1),
       .rresp_m1       (i_axi_rresp_m1),
       .rlast_m1       (i_axi_rlast_m1),
       .rready_m1      (gm_wr_rready),
       .awvalid_m2     (gm_rd_awvalid),
       .awaddr_m2      (gm_rd_awaddr),
       .awid_m2        (gm_rd_awid),
       .awlen_m2       (gm_rd_awlen),
       .awsize_m2      (gm_rd_awsize),
       .awburst_m2     (gm_rd_awburst),
       .awlock_m2      (gm_rd_awlock),
       .awcache_m2     (gm_rd_awcache),
       .awprot_m2      (gm_rd_awprot),
       .awready_m2     (i_axi_awready_m2),
       .wvalid_m2      (gm_rd_wvalid),
       .wid_m2         (gm_rd_wid),
       .wdata_m2       (gm_rd_wdata),
       .wstrb_m2       (gm_rd_wstrb),
       .wlast_m2       (gm_rd_wlast),
       .wready_m2      (i_axi_wready_m2),
       .bvalid_m2      (i_axi_bvalid_m2),
       .bid_m2         (i_axi_bid_m2),
       .bresp_m2       (i_axi_bresp_m2),
       .bready_m2      (gm_rd_bready),
       .arvalid_m2     (gm_rd_arvalid),
       .arid_m2        (gm_rd_arid),
       .araddr_m2      (gm_rd_araddr),
       .arlen_m2       (gm_rd_arlen),
       .arsize_m2      (gm_rd_arsize),
       .arburst_m2     (gm_rd_arburst),
       .arlock_m2      (gm_rd_arlock),
       .arcache_m2     (gm_rd_arcache),
       .arprot_m2      (gm_rd_arprot),
       .arready_m2     (i_axi_arready_m2),
       .rvalid_m2      (i_axi_rvalid_m2),
       .rid_m2         (i_axi_rid_m2),
       .rdata_m2       (i_axi_rdata_m2),
       .rresp_m2       (i_axi_rresp_m2),
       .rlast_m2       (i_axi_rlast_m2),
       .rready_m2      (gm_rd_rready),
       .awvalid_s1     (i_axi_awvalid_s1),
       .awaddr_s1      (i_axi_awaddr_s1),
       .awid_s1        (i_axi_awid_s1),
       .awlen_s1       (i_axi_awlen_s1),
       .awsize_s1      (i_axi_awsize_s1),
       .awburst_s1     (i_axi_awburst_s1),
       .awlock_s1      (i_axi_awlock_s1),
       .awcache_s1     (i_axi_awcache_s1),
       .awprot_s1      (i_axi_awprot_s1),
       .awready_s1     (i_axi_x2h_awready),
       .wvalid_s1      (i_axi_wvalid_s1),
       .wid_s1         (i_axi_wid_s1),
       .wdata_s1       (i_axi_wdata_s1),
       .wstrb_s1       (i_axi_wstrb_s1),
       .wlast_s1       (i_axi_wlast_s1),
       .wready_s1      (i_axi_x2h_wready),
       .bvalid_s1      (i_axi_x2h_bvalid),
       .bid_s1         (i_axi_x2h_bid),
       .bresp_s1       (i_axi_x2h_bresp),
       .bready_s1      (i_axi_bready_s1),
       .arvalid_s1     (i_axi_arvalid_s1),
       .arid_s1        (i_axi_arid_s1),
       .araddr_s1      (i_axi_araddr_s1),
       .arlen_s1       (i_axi_arlen_s1),
       .arsize_s1      (i_axi_arsize_s1),
       .arburst_s1     (i_axi_arburst_s1),
       .arlock_s1      (i_axi_arlock_s1),
       .arcache_s1     (i_axi_arcache_s1),
       .arprot_s1      (i_axi_arprot_s1),
       .arready_s1     (i_axi_x2h_arready),
       .rvalid_s1      (i_axi_x2h_rvalid),
       .rid_s1         (i_axi_x2h_rid),
       .rdata_s1       (i_axi_x2h_rdata),
       .rresp_s1       (i_axi_x2h_rresp),
       .rlast_s1       (i_axi_x2h_rlast),
       .rready_s1      (i_axi_rready_s1),
       .dbg_awid_s0    (i_axi_dbg_awid_s0),
       .dbg_awaddr_s0  (i_axi_dbg_awaddr_s0),
       .dbg_awlen_s0   (i_axi_dbg_awlen_s0),
       .dbg_awsize_s0  (i_axi_dbg_awsize_s0),
       .dbg_awburst_s0 (i_axi_dbg_awburst_s0),
       .dbg_awlock_s0  (i_axi_dbg_awlock_s0),
       .dbg_awcache_s0 (i_axi_dbg_awcache_s0),
       .dbg_awprot_s0  (i_axi_dbg_awprot_s0),
       .dbg_awvalid_s0 (i_axi_dbg_awvalid_s0),
       .dbg_awready_s0 (i_axi_dbg_awready_s0),
       .dbg_wid_s0     (i_axi_dbg_wid_s0),
       .dbg_wdata_s0   (i_axi_dbg_wdata_s0),
       .dbg_wstrb_s0   (i_axi_dbg_wstrb_s0),
       .dbg_wlast_s0   (i_axi_dbg_wlast_s0),
       .dbg_wvalid_s0  (i_axi_dbg_wvalid_s0),
       .dbg_wready_s0  (i_axi_dbg_wready_s0),
       .dbg_bid_s0     (i_axi_dbg_bid_s0),
       .dbg_bresp_s0   (i_axi_dbg_bresp_s0),
       .dbg_bvalid_s0  (i_axi_dbg_bvalid_s0),
       .dbg_bready_s0  (i_axi_dbg_bready_s0),
       .dbg_arid_s0    (i_axi_dbg_arid_s0),
       .dbg_araddr_s0  (i_axi_dbg_araddr_s0),
       .dbg_arlen_s0   (i_axi_dbg_arlen_s0),
       .dbg_arsize_s0  (i_axi_dbg_arsize_s0),
       .dbg_arburst_s0 (i_axi_dbg_arburst_s0),
       .dbg_arlock_s0  (i_axi_dbg_arlock_s0),
       .dbg_arcache_s0 (i_axi_dbg_arcache_s0),
       .dbg_arprot_s0  (i_axi_dbg_arprot_s0),
       .dbg_arvalid_s0 (i_axi_dbg_arvalid_s0),
       .dbg_arready_s0 (i_axi_dbg_arready_s0),
       .dbg_rid_s0     (i_axi_dbg_rid_s0),
       .dbg_rdata_s0   (i_axi_dbg_rdata_s0),
       .dbg_rresp_s0   (i_axi_dbg_rresp_s0),
       .dbg_rvalid_s0  (i_axi_dbg_rvalid_s0),
       .dbg_rlast_s0   (i_axi_dbg_rlast_s0),
       .dbg_rready_s0  (i_axi_dbg_rready_s0),
       .remap_n        (i_axi_remap_n));

   i_axi_x2h_DW_axi_x2h i_axi_x2h
      (.rdata    (i_axi_x2h_rdata),
       .bresp    (i_axi_x2h_bresp),
       .rresp    (i_axi_x2h_rresp),
       .bid      (i_axi_x2h_bid),
       .rid      (i_axi_x2h_rid),
       .awready  (i_axi_x2h_awready),
       .wready   (i_axi_x2h_wready),
       .bvalid   (i_axi_x2h_bvalid),
       .arready  (i_axi_x2h_arready),
       .rlast    (i_axi_x2h_rlast),
       .rvalid   (i_axi_x2h_rvalid),
       .mhaddr   (i_axi_x2h_mhaddr),
       .mhburst  (i_axi_x2h_mhburst),
       .cactive  (i_axi_x2h_cactive),
       .mhbusreq (i_axi_x2h_mhbusreq),
       .mhlock   (i_axi_x2h_mhlock),
       .mhprot   (i_axi_x2h_mhprot),
       .mhsize   (i_axi_x2h_mhsize),
       .mhtrans  (i_axi_x2h_mhtrans),
       .mhwdata  (i_axi_x2h_mhwdata),
       .mhwrite  (i_axi_x2h_mhwrite),
       .aclk     (ACLK_aclk),
       .aresetn  (ARESETn_aresetn),
       .awaddr   (i_axi_awaddr_s1),
       .wdata    (i_axi_wdata_s1),
       .araddr   (i_axi_araddr_s1),
       .awvalid  (i_axi_awvalid_s1),
       .wlast    (i_axi_wlast_s1),
       .wvalid   (i_axi_wvalid_s1),
       .bready   (i_axi_bready_s1),
       .arvalid  (i_axi_arvalid_s1),
       .rready   (i_axi_rready_s1),
       .awburst  (i_axi_awburst_s1),
       .awlock   (i_axi_awlock_s1),
       .arburst  (i_axi_arburst_s1),
       .arlock   (i_axi_arlock_s1),
       .awsize   (i_axi_awsize_s1),
       .awprot   (i_axi_awprot_s1),
       .arsize   (i_axi_arsize_s1),
       .arprot   (i_axi_arprot_s1),
       .awid     (i_axi_awid_s1),
       .wid      (i_axi_wid_s1),
       .awlen    (i_axi_awlen_s1),
       .awcache  (i_axi_awcache_s1),
       .wstrb    (i_axi_wstrb_s1),
       .arid     (i_axi_arid_s1),
       .arlen    (i_axi_arlen_s1),
       .arcache  (i_axi_arcache_s1),
       .mhclk    (HCLK_hclk),
       .mhresetn (HRESETn_hresetn),
       .mhgrant  (i_ahb_hgrant_m1),
       .mhrdata  (i_ahb_hrdata),
       .mhready  (i_ahb_hready),
       .mhresp   (i_ahb_hresp));

   i_memctl_DW_memctl i_memctl
      (.hready_resp           (i_memctl_hready_resp),
       .hresp                 (i_memctl_hresp),
       .hrdata                (i_memctl_hrdata),
       .s_ras_n               (i_memctl_s_ras_n),
       .s_cas_n               (i_memctl_s_cas_n),
       .s_cke                 (i_memctl_s_cke),
       .s_wr_data             (i_memctl_s_wr_data),
       .s_addr                (i_memctl_s_addr),
       .s_bank_addr           (i_memctl_s_bank_addr),
       .s_dout_valid          (i_memctl_s_dout_valid),
       .s_sel_n               (i_memctl_s_sel_n),
       .s_dqm                 (i_memctl_s_dqm),
       .s_we_n                (i_memctl_s_we_n),
       .s_sa                  (i_memctl_s_sa),
       .s_scl                 (i_memctl_s_scl),
       .s_rd_ready            (i_memctl_s_rd_ready),
       .s_rd_start            (i_memctl_s_rd_start),
       .s_rd_pop              (i_memctl_s_rd_pop),
       .s_rd_end              (i_memctl_s_rd_end),
       .s_rd_dqs_mask         (i_memctl_s_rd_dqs_mask),
       .s_cas_latency         (i_memctl_s_cas_latency),
       .s_read_pipe           (i_memctl_s_read_pipe),
       .s_sda_out             (i_memctl_s_sda_out),
       .s_sda_oe_n            (i_memctl_s_sda_oe_n),
       .gpo                   (i_memctl_gpo),
       .debug_ad_bank_addr    (i_memctl_debug_ad_bank_addr),
       .debug_ad_row_addr     (i_memctl_debug_ad_row_addr),
       .debug_ad_col_addr     (i_memctl_debug_ad_col_addr),
       .debug_ad_sf_bank_addr (i_memctl_debug_ad_sf_bank_addr),
       .debug_ad_sf_row_addr  (i_memctl_debug_ad_sf_row_addr),
       .debug_ad_sf_col_addr  (i_memctl_debug_ad_sf_col_addr),
       .debug_hiu_addr        (i_memctl_debug_hiu_addr),
       .debug_sm_burst_done   (i_memctl_debug_sm_burst_done),
       .debug_sm_pop_n        (i_memctl_debug_sm_pop_n),
       .debug_sm_push_n       (i_memctl_debug_sm_push_n),
       .debug_smc_cs          (i_memctl_debug_smc_cs),
       .debug_ref_req         (i_memctl_debug_ref_req),
       .hclk                  (HCLK_hclk),
       .hresetn               (HRESETn_hresetn),
       .haddr                 (i_ahb_haddr),
       .hsel_mem              (i_ahb_hsel_s1),
       .hsel_reg              (i_ahb_hsel_s2),
       .hwrite                (i_ahb_hwrite),
       .htrans                (i_ahb_htrans),
       .hsize                 (i_ahb_hsize),
       .hburst                (i_ahb_hburst),
       .hready                (i_ahb_hready),
       .hwdata                (i_ahb_hwdata),
       .s_rd_data             (i_memctl_s_rd_data),
       .s_sda_in              (i_memctl_s_sda_in),
       .gpi                   (i_memctl_gpi),
       .remap                 (i_memctl_remap),
       .power_down            (i_memctl_power_down),
       .clear_sr_dp           (i_memctl_clear_sr_dp),
       .big_endian            (1'b0));



endmodule
