//-------------------------------------------------------------------
//
//  Filename      : GFP_clkgen.v
//  Author        : Huang Lei Lei
//  Created       : 2015-09-09
//  Description   : clk generator of whole system
//
//-------------------------------------------------------------------

`include "GFP_defines.v"

module GFP_clkgen (
  // clk & rst in
  board_clk       ,
  board_rst       ,
  // clk & rst out
  sys_clk         ,
  sys_rst         ,
  vga_ctrl_clk    ,
  vga_ctrl_rst
  );


//*** INPUT/OUTPUT DECLARATION *************************************************

  // clk & rst in
  input         board_clk     ;
  input         board_rst     ;
  // clk & rst out
  output        sys_clk       ;
  output        sys_rst       ;
  output        vga_ctrl_clk  ;
  output        vga_ctrl_rst  ;


//*** WIRE & REG DECLARATION ***************************************************

  wire          pll_locked    ;


//*** MAIN BODY ****************************************************************

  // clk
  pll pll0 (
    .inclk0    ( board_clk       ),
    .areset    ( board_rst       ),
    .c0        ( sys_clk         ),
    .c1        ( vga_ctrl_clk    ),
    .locked    ( pll_locked      )
    );

  // sys_rst
  reg [15 :0] sys_rst_shr ;
  always @(posedge sys_clk) begin
    if( board_rst )
      sys_rst_shr <= 16'hffff ;
    else begin
      sys_rst_shr <= {sys_rst_shr[14:0], ~(pll_locked)} ;
    end
  end
  assign sys_rst = sys_rst_shr[15] ;

  // vga_ctrl_rst
  reg [15 :0] vga_ctrl_rst_shr ;
  always @(posedge vga_ctrl_clk) begin
    if( board_rst )
      vga_ctrl_rst_shr <= 16'hffff ;
    else begin
      vga_ctrl_rst_shr <= {vga_ctrl_rst_shr[14:0], ~(pll_locked)} ;
    end
  end
  assign vga_ctrl_rst = vga_ctrl_rst_shr[15] ;

endmodule
